KR100237669B1 - Multi layer ceramic package - Google Patents

Multi layer ceramic package Download PDF

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Publication number
KR100237669B1
KR100237669B1 KR1019920022699A KR920022699A KR100237669B1 KR 100237669 B1 KR100237669 B1 KR 100237669B1 KR 1019920022699 A KR1019920022699 A KR 1019920022699A KR 920022699 A KR920022699 A KR 920022699A KR 100237669 B1 KR100237669 B1 KR 100237669B1
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South Korea
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layer
ceramic package
package
multilayer ceramic
metal
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KR1019920022699A
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Korean (ko)
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KR940012586A (en
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심성민
김영대
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

반도체 칩과 다층 세라믹 패키지의 결합을 위해서 칩 그리고 메탈리드와 와이어 또는 열압착으로 연결되는 패키지의 금속화층은 세라믹 기판(1) 위에 텅스텐(W)층과, 그 위에 TiN층과, 그 위에 Au층의 다층으로 구성되며, Au층은 외부와 연결되며 열공정시 상기 Ti가 Au 표면으로 확산되지 않도록 한 것을 특징으로 하는 다층 세라믹 패키지.To bond the semiconductor chip and the multilayer ceramic package, the metallization layer of the chip and the metal lead and the package connected by wire or thermocompression is made of a tungsten (W) layer on the ceramic substrate 1, a TiN layer thereon, and an Au layer thereon. The multilayer ceramic package, characterized in that the Au layer is connected to the outside and the Ti is not diffused to the Au surface during the thermal process.

Description

다층 세라믹 패키지Multilayer ceramic package

제1도는 다층 세라믹 패키지(MLP)의 사시도.1 is a perspective view of a multilayer ceramic package (MLP).

제2도는 MLP의 부분적으로 단면이 도시된 측면도.2 is a side view showing a partial cross section of the MLP.

제3(a)도, 제3(b)도는 본 발명에 따라서 제2도의 A부분인 금속화층의 구조에 대한 단면도이다.3 (a) and 3 (b) are sectional views of the structure of the metallization layer which is part A of FIG. 2 in accordance with the present invention.

본 발명은 반도체 장치를 위한 다층 세라믹 패키지에 관한 것으로, 특히 외부와의 연결에 필요한 금속 리드와 패드의 연결을 위해서 다층 구종의 금속패드를 형성한 다층 세라믹 패키지 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic package for a semiconductor device, and more particularly, to a multilayer ceramic package structure in which metal pads of multiple layers are formed to connect metal leads and pads necessary for external connection.

반도체 집적회로는 기판상에 형성되고 금속공정을 거쳐 금속패드는 외부 연결을 위해 마련된다. 이 부분은 형성된 집적회로의 부분과 외부의 다른 소자 내지는 디바이스에 도전체를 매개로 연결된다.The semiconductor integrated circuit is formed on a substrate and the metal pad is provided for external connection through a metal process. This part is connected to a part of the formed integrated circuit and other external elements or devices via a conductor.

상기 다이 분리된 칩은 세라믹 패키지에 결합되어 하나의 디바이스로 사용되는데 일반적으로 세라믹 패키지는 제조방법과 그 구조에 따라서는 다층 세라믹 패키지가 활용되고 있으며 이것은 세라믹 패키지 자체가 금속 공정을 거쳐 형상화되고 이에 상기 칩의 금속 연결부가 서로 도전체로 연결되어 조립되는 방식을 취하는 것이다. 다층 세라믹 패키지는 그 자체가 메탈라이제이션 시스템을 갖고 있고 이로 인해 요구되는 바는 첫째, 전력 손실의 최소화, 둘째 열악한 환경에서의 안정성, 셋째로는 금속화 시스템들간에 적절한 조합 및 용이한 제조공정이다. 이러한 관점에서 Au/Ni 금속화 시스템이 잘 쓰이고 있다.The die separated chip is coupled to a ceramic package and used as a device. In general, a multilayer ceramic package is utilized according to a manufacturing method and a structure thereof, and the ceramic package itself is shaped through a metal process. The metal connections of the chip are connected to each other by a conductor and assembled. The multilayer ceramic package itself has a metallization system, which requires, firstly, minimizing power loss, secondly stability in harsh environments, and thirdly a suitable combination and easy manufacturing process between metallization systems. . In this respect, Au / Ni metallization systems are well used.

제1도는 MLP에 의한 외관을 보인 사시도로서 1은 세라믹 기판이며, 2는 다이 접착 표면, 3은 메탈리드가 안착되는 영역을 가르킨다. 이러한 부분은 통상은 수직으로 볼 때 Au/Ni/W의 3층 구조로 하여 접촉 영역의 공정 중 전기적 특성을 좋게 하고 있다. 즉 각 층간에 접착(adhesion)을 형성시켜 주고 층간에 유사한 열팽창 계수를 제공하여 열방사에 따른 열적 스트레스를 방지하고 층간의 확산 장벽으로서 역할을 한다.FIG. 1 is a perspective view showing the appearance by MLP, where 1 is a ceramic substrate, 2 is a die attaching surface, and 3 is a region where a metal lead is seated. This part usually has a three-layer structure of Au / Ni / W when viewed vertically to improve the electrical characteristics during the process of the contact region. That is, it forms an adhesion between the layers and provides a similar coefficient of thermal expansion between the layers to prevent thermal stress due to thermal radiation and act as a diffusion barrier between the layers.

그러나, 이러한 구조의 금속패드는 외부 리이드와 와이어 본딩으로 연결되는데 통상은 열압착에 의한 방식이 흔히 쓰인다. 따라서 금속층내의 Ni이 열에 의한 영향으로 Au층 표면으로 확산, 석출되어 메탈리드 실링이 잘 이루어지지 않는 문제를 야기 시켜왔다. 즉, Ni이 Au층 표면으로 석출되면서 대기중의 산소와 반응하여 Ni 산화물을 형성시키게 되고 메탈 리드 실링 공정에서 불량을 야기시키는 것이다. 더욱이 다이 접착후 도전 라인의 금속화 구조에서도 동일한 문제를 일으키고 와이어 본딩시 본딩이 잘 안되는 현상이 일어난다.However, the metal pad of this structure is connected to the outer lead and wire bonding, usually by a thermal compression method. Therefore, Ni in the metal layer has been diffused and precipitated on the surface of the Au layer under the influence of heat, causing a problem that the metal lead sealing is not made well. That is, Ni precipitates on the surface of the Au layer and reacts with oxygen in the air to form Ni oxide, which causes defects in the metal lead sealing process. Moreover, the same problem occurs in the metallization structure of the conductive line after die bonding, and a phenomenon in which bonding is difficult during wire bonding occurs.

본 발명 이러한 문제를 해결하기 위해 이루어진 것으로 본 발명의 목적은 반도체 칩의 금속 패드 구조내에 확산 방지 장벽을 개재시켜 와이어 본딩과 같은 후속 공정에 의해서 접촉 불량이 야기되는 문제를 방지한 금속패드 구조를 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to provide a metal pad structure which prevents a problem of contact failure caused by a subsequent process such as wire bonding by interposing a diffusion barrier in the metal pad structure of a semiconductor chip. It is.

본 발명의 목적을 달성하는 반도체 칩의 금속패드 구조는 반도체 칩과 다층 세라믹 패키지의 결합을 위해서 칩 그리고 메탈리드와 와이어 또는 열압착으로 연결되는 패키지의 금속화층은 세라믹 기판(1) 위에 텅스텐(W)층과, 그 위에 TiN층과, 그 위에 Au층의 다층으로 구성되며, Au층은 외부와 연결되며 열공정시 상기 Ti가 Au 표면으로 확산되지 않도록 한 것을 특징으로 한다.The metal pad structure of the semiconductor chip to achieve the object of the present invention is a metallization layer of the chip and the metallization and the package to be connected by wire or thermocompression bonding for the semiconductor chip and the multilayer ceramic package is tungsten (W) on the ceramic substrate (1) ) Layer, a TiN layer thereon, and a multilayered Au layer thereon, and the Au layer is connected to the outside and prevents the Ti from diffusing to the Au surface during the thermal process.

본 발명에 대한 상세한 내용을 첨부한 도면을 참고하여 이하 설명한다.Detailed description of the present invention will be described below with reference to the accompanying drawings.

제2도는 MLP에 대해 부분 단면을 표시한 측면 외관도로서, 4는 다이, 5는 메탈 리드, 6은 다층 적층된 알루미나층, 7은 금속합금인 코바(kovar), 8은 금속 와이어, 9는 솔더, 10은 다층 금속층을 가르킨다.2 is a side view showing a partial cross section of the MLP, 4 is a die, 5 is a metal lead, 6 is a multi-layered alumina layer, 7 is a metal alloy kovar (kovar), 8 is a metal wire, 9 is Solder, 10, refers to a multilayer metal layer.

칩(4)의 연결된 부분과 패키지의 다층 금속층(10)은 와이어(8)로 서로 연결되는데 언급한 문제의 해결을 위해서 도면에서 A로 표시된 부분은 제3(a)도, 제3(b)도에 보듯이 다층의 층으로 구성된 구조를 갖는다.The connected portion of the chip 4 and the multi-layered metal layer 10 of the package are connected to each other by a wire 8. In order to solve the above mentioned problem, the portion indicated by A in the drawing is also referred to as the third (a) and the third (b). As shown in the figure, it has a structure composed of multiple layers.

세라믹 기판(S) 위에 차례대로 텅스텐(W)층(11), Ni층(12), TiN층(14), 그리고 Au층(13)으로 형성되어 금속 층을 형성하게 된다. 본 실예에서는 TiN층(14)을 5000Å 두께로 형성하였으며 금속층 형성후 300℃~500℃의 열처리를 행한 후 칩과 와이어 본딩을 행하였다. 신장력을 알기 위해서 Au 표면의 Ni 함량에 대한 풀 강도(pull stregth)를 보면 반비례되는 특성 곡선을 얻는데 Ni 함량이 많이 발견될수록 강도는 저하된다.The tungsten (W) layer 11, the Ni layer 12, the TiN layer 14, and the Au layer 13 are sequentially formed on the ceramic substrate S to form a metal layer. In this example, the TiN layer 14 was formed to have a thickness of 5000 kPa, and after the formation of the metal layer, heat treatment was performed at 300 ° C. to 500 ° C., and chip and wire bonding was performed. In order to know the stretching force, the pull stregth of the Ni content on the Au surface yields an inverse characteristic curve. The more the Ni content is found, the lower the strength.

본 발명에서 Au층 밑의 Ni 층의 확산이 억제될 수 있는데 이에 따라 상기 특성 곡선의 정보로부터 강도가 유지됨을 알 수 있으며, 또한 메탈리드 실링이나 와이어 본딩의 질을 향상시키게 된다.In the present invention, the diffusion of the Ni layer under the Au layer can be suppressed. Accordingly, it can be seen that the strength is maintained from the information of the characteristic curve, and the quality of the metal lead sealing or the wire bonding is improved.

제3(b)도는 제3(a)도와 유사하나 단지 TiN층이 없는 것의 실시예로서 Ni층에 대해서 O2플라즈마 처리로 Ni 산화층을 형성하여 Ni층(12)의 Ni 확산을 억제시켜 본 발명의 목적을 달성시킨다.FIG. 3 (b) is similar to that of FIG. 3 (a), but only in the absence of a TiN layer, an Ni oxide layer is formed on the Ni layer by O 2 plasma treatment to suppress Ni diffusion of the Ni layer 12. To achieve the purpose.

종래기술에서 Ni 석출 때문에 메탈리드의 실링에 문제가 있었으나 본 발명에 따라서 질이 우수한 MLP가 얻어지게 된다.In the prior art, there was a problem in the sealing of the metal lead due to Ni precipitation, but according to the present invention, an excellent MLP is obtained.

Claims (3)

반도체 칩과 다층 세라믹 패키지의 결합을 위해서 칩 그리고 메탈리드와 와이어 또는 열압착으로 연결되는 패키지의 금속화층은 세라믹 기판(1) 위에 텅스텐(W)층 위에 형성되어 있는 Ni층, 상기 Ni층 위에 형성되어 있는 TiN층 및 상기 TiN층 위에 형성되어 있으며 외부와 연결되어 있는 Au층의 다층을 포함함으로써, 열공정시 상기 Ni가 Au 표면으로 확산되지 않도록 한 것을 특징으로 하는 다층 세라믹 패키지.In order to bond the semiconductor chip and the multilayer ceramic package, the metallization layer of the chip and the metal lead and the package connected by wire or thermocompression bonding is formed on the Ni layer formed on the tungsten (W) layer on the ceramic substrate 1 and on the Ni layer. The multilayer ceramic package, characterized in that the Ni layer is formed on the TiN layer and the TiN layer and connected to the outside, so that the Ni does not diffuse to the Au surface during the thermal process. 반도체 칩과 다층 세라믹 패키지의 결합을 위해서 칩 그리고 메탈리드와 와이어 또는 열압착으로 연결되는 패키지의 금속화층은 세라믹 기판(1) 위에 형성되어 있는 텅스텐(W)층, 상기 텅스텐(W)층 위에 형성되어 있는 Ni층, 상기 Ni층 위에 형성되어 있는 Ni 산화층 및 상기 Ni 산화층 위에 형성되어 있으며 외부와 연결되어 있는 Au층의 다층을 포함함으로써, 열공정시 상기 Ni가 Au 표면으로 확산되지 않도록 한 것을 특징으로 하는 다층 세라믹 패키지.In order to bond the semiconductor chip and the multilayer ceramic package, the metallization layer of the chip and the metal lead and the package connected by wire or thermocompression bonding is formed on the tungsten (W) layer formed on the ceramic substrate 1 and the tungsten (W) layer. By including a Ni layer, a Ni oxide layer formed on the Ni layer and a multilayer of Au layer formed on the Ni oxide layer and connected to the outside, the Ni is prevented from diffusing to the Au surface during the thermal process. Multi-layer ceramic package. 제2항에서, 상기 Ni 산화층은 상기 Ni층을 O2플라즈마 처리함으로써 형성하는 것을 특징으로 하는 다층 세라믹 패키지.The multilayer ceramic package of claim 2 , wherein the Ni oxide layer is formed by O 2 plasma treatment of the Ni layer.
KR1019920022699A 1992-11-28 1992-11-28 Multi layer ceramic package KR100237669B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010117107A1 (en) * 2009-04-09 2010-10-14 ㈜와이에스썸텍 Method for forming insulating layers for high thermal radiation of metal substrate and metal substrate manufactured thereby

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137654A (en) * 1987-11-25 1989-05-30 Kyocera Corp Chip carrier
JPH0311653A (en) * 1989-06-07 1991-01-18 Nec Yamagata Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137654A (en) * 1987-11-25 1989-05-30 Kyocera Corp Chip carrier
JPH0311653A (en) * 1989-06-07 1991-01-18 Nec Yamagata Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010117107A1 (en) * 2009-04-09 2010-10-14 ㈜와이에스썸텍 Method for forming insulating layers for high thermal radiation of metal substrate and metal substrate manufactured thereby

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