KR940012542A - 좁은 베이스 효과를 제거하는 트랜지스터 제조방법 - Google Patents

좁은 베이스 효과를 제거하는 트랜지스터 제조방법 Download PDF

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Publication number
KR940012542A
KR940012542A KR1019930023863A KR930023863A KR940012542A KR 940012542 A KR940012542 A KR 940012542A KR 1019930023863 A KR1019930023863 A KR 1019930023863A KR 930023863 A KR930023863 A KR 930023863A KR 940012542 A KR940012542 A KR 940012542A
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South Korea
Prior art keywords
wafer
transistor
applying
region
disposed
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KR1019930023863A
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아르 파렌코프 도그
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존 엠. 클락 3세
내쇼날 세미컨덕터 코포레이션
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Application filed by 존 엠. 클락 3세, 내쇼날 세미컨덕터 코포레이션 filed Critical 존 엠. 클락 3세
Publication of KR940012542A publication Critical patent/KR940012542A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

제어된 베타 및 제어된 고항복전압을 갖는 NPN 트랜지스터를 형성하는 제조방법에 개시되어 있다. 에미터 및 베이스 불순물은 실리콘 웨이퍼상의 전계산화물내에 사진석판인쇄술로 형성된 홀(hole)을 통해 이온 주입된다. 에미터 불순물을 도포하는 단계 및 베이스 불순물을 도포하는 단계 사이에서 산화물을 에칭한다.

Description

좁은 베이스 효과를 제거하는 트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 산화물을 에칭한 다음 제1도에 도시된 바와같이 에미터를 형성하는 본 발명의 단계 이후에 베이스 주입을 보여주는 반도체 웨이퍼 부분에 대한 단면도.
제4도는 제3도 트랜지스터의 표면 구조를 보여주는 반도체 웨이퍼 부분에 대한 도면.

Claims (1)

  1. NPN 트랜지스터가 형성될 N형 영역을 지니는 실리콘 웨이퍼를 제공하는 단계, 상기 트랜지스터가 배치될 영역을 제외하고 상기 웨이퍼상에 전계 산화물을 형성하는 단계, 상기 트랜지스터 에미터 영역이 배치될 상기 웨이퍼상에 배치된 사진석판 인쇄술로 형성된 개구부를 지니는 상기 웨이퍼상에 제1의 마스킹 레지스트를 도포하는 단계, 상기 제1의 마스킹 레지스트내의 개구부분 내측에 N형 불순물을 도포시키고 상기 N형 불순물의 양을 제어하여 소기의 트랜지스터의 에미터 도우핑을 제공하는 단계, 상기 트랜지스터 베이스 영역이 배치될 웨이퍼 부분상에 배치된 사진석판 인쇄술로 형성된 개구부분을 지니는 상기 웨이퍼상에 제2마스킹 레지스트를 도포하는 단계, 상기 제2의 마스킹 레지스터내의 개구부분에 내측에 P형 불순물을 도포하고 상기 P형 불순물의 양을 제어하여 소기의 트랜지스터 베이스 도우핑을 제공하는 단계, 및 상기 웨이퍼를 가열하여 P 및 N형 불순물을 활성화시켜 이를 상기 웨이퍼에 확산시키는 단계를 포함하여, 실리콘 웨이퍼상에 NPN 트랜지스터를 제조하는 방법에 있어서, P형 불순물을 도입하는 단계이전에 상기 실리콘에 대하여 선택적으로 상기 산화물을 침식시키는 에칭을 상기 웨이퍼에 이행하는 단계를 포함하는 개선된 NPN 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930023863A 1992-11-12 1993-11-11 좁은 베이스 효과를 제거하는 트랜지스터 제조방법 KR940012542A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US97476992A 1992-11-12 1992-11-12
US92-07/974,769 1992-11-12

Publications (1)

Publication Number Publication Date
KR940012542A true KR940012542A (ko) 1994-06-23

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ID=25522417

Family Applications (1)

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KR1019930023863A KR940012542A (ko) 1992-11-12 1993-11-11 좁은 베이스 효과를 제거하는 트랜지스터 제조방법

Country Status (4)

Country Link
EP (1) EP0605946B1 (ko)
JP (1) JPH06216140A (ko)
KR (1) KR940012542A (ko)
DE (1) DE69323614T2 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864162A (en) * 1993-07-12 1999-01-26 Peregrine Seimconductor Corporation Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US5863823A (en) * 1993-07-12 1999-01-26 Peregrine Semiconductor Corporation Self-aligned edge control in silicon on insulator
US5930638A (en) * 1993-07-12 1999-07-27 Peregrine Semiconductor Corp. Method of making a low parasitic resistor on ultrathin silicon on insulator
JP5195077B2 (ja) * 2008-06-26 2013-05-08 株式会社デンソー バイポーラトランジスタの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2728845A1 (de) * 1977-06-27 1979-01-18 Siemens Ag Verfahren zum herstellen eines hochfrequenztransistors
DE3047140A1 (de) * 1980-12-15 1982-07-22 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten halbleiterschaltung
JPS57149770A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Manufacture of semiconductor device
US4465528A (en) * 1981-07-15 1984-08-14 Fujitsu Limited Method of producing a walled emitter semiconductor device

Also Published As

Publication number Publication date
EP0605946A3 (en) 1995-04-19
DE69323614T2 (de) 1999-06-17
EP0605946B1 (en) 1999-02-24
EP0605946A2 (en) 1994-07-13
JPH06216140A (ja) 1994-08-05
DE69323614D1 (de) 1999-04-01

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