DE69323614D1 - Schmale Basis-Effekte vermeidendes Verfahren für einen Transistor - Google Patents
Schmale Basis-Effekte vermeidendes Verfahren für einen TransistorInfo
- Publication number
- DE69323614D1 DE69323614D1 DE69323614T DE69323614T DE69323614D1 DE 69323614 D1 DE69323614 D1 DE 69323614D1 DE 69323614 T DE69323614 T DE 69323614T DE 69323614 T DE69323614 T DE 69323614T DE 69323614 D1 DE69323614 D1 DE 69323614D1
- Authority
- DE
- Germany
- Prior art keywords
- transistor
- basic effects
- avoiding process
- narrow basic
- effects avoiding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US97476992A | 1992-11-12 | 1992-11-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69323614D1 true DE69323614D1 (de) | 1999-04-01 |
DE69323614T2 DE69323614T2 (de) | 1999-06-17 |
Family
ID=25522417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69323614T Expired - Fee Related DE69323614T2 (de) | 1992-11-12 | 1993-10-20 | Schmale Basis-Effekte vermeidendes Verfahren für einen Transistor |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0605946B1 (de) |
JP (1) | JPH06216140A (de) |
KR (1) | KR940012542A (de) |
DE (1) | DE69323614T2 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930638A (en) * | 1993-07-12 | 1999-07-27 | Peregrine Semiconductor Corp. | Method of making a low parasitic resistor on ultrathin silicon on insulator |
US5864162A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Seimconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
US5863823A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Semiconductor Corporation | Self-aligned edge control in silicon on insulator |
JP5195077B2 (ja) * | 2008-06-26 | 2013-05-08 | 株式会社デンソー | バイポーラトランジスタの製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2728845A1 (de) * | 1977-06-27 | 1979-01-18 | Siemens Ag | Verfahren zum herstellen eines hochfrequenztransistors |
DE3047140A1 (de) * | 1980-12-15 | 1982-07-22 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen einer monolithisch integrierten halbleiterschaltung |
JPS57149770A (en) * | 1981-03-11 | 1982-09-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US4465528A (en) * | 1981-07-15 | 1984-08-14 | Fujitsu Limited | Method of producing a walled emitter semiconductor device |
-
1993
- 1993-10-20 EP EP93308354A patent/EP0605946B1/de not_active Expired - Lifetime
- 1993-10-20 DE DE69323614T patent/DE69323614T2/de not_active Expired - Fee Related
- 1993-11-11 KR KR1019930023863A patent/KR940012542A/ko not_active Application Discontinuation
- 1993-11-12 JP JP5283497A patent/JPH06216140A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0605946A3 (de) | 1995-04-19 |
EP0605946A2 (de) | 1994-07-13 |
EP0605946B1 (de) | 1999-02-24 |
DE69323614T2 (de) | 1999-06-17 |
KR940012542A (ko) | 1994-06-23 |
JPH06216140A (ja) | 1994-08-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |