KR940008358B1 - 매입 유전체상에 형성된 배선층 및 그 제조방법 - Google Patents

매입 유전체상에 형성된 배선층 및 그 제조방법 Download PDF

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Publication number
KR940008358B1
KR940008358B1 KR1019880003697A KR880003697A KR940008358B1 KR 940008358 B1 KR940008358 B1 KR 940008358B1 KR 1019880003697 A KR1019880003697 A KR 1019880003697A KR 880003697 A KR880003697 A KR 880003697A KR 940008358 B1 KR940008358 B1 KR 940008358B1
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KR
South Korea
Prior art keywords
grooves
semiconductor substrate
wiring layer
oxide film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019880003697A
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English (en)
Korean (ko)
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KR890005844A (ko
Inventor
다까시 우라베
요오이찌 도비다
Original Assignee
미쓰비시 뎅끼 가부시끼가이샤
시기 모리야
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Publication date
Application filed by 미쓰비시 뎅끼 가부시끼가이샤, 시기 모리야 filed Critical 미쓰비시 뎅끼 가부시끼가이샤
Priority to JP63255747A priority Critical patent/JPH01175554A/ja
Priority to US07/292,557 priority patent/US4925252A/en
Publication of KR890005844A publication Critical patent/KR890005844A/ko
Application granted granted Critical
Publication of KR940008358B1 publication Critical patent/KR940008358B1/ko
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H10W10/0123—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves using auxiliary pillars in the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
KR1019880003697A 1987-09-08 1988-04-01 매입 유전체상에 형성된 배선층 및 그 제조방법 Expired - Fee Related KR940008358B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63255747A JPH01175554A (ja) 1987-12-30 1988-10-11 自動車の制御装置
US07/292,557 US4925252A (en) 1987-12-30 1988-12-30 Automobile brake system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62225039A JPS6467945A (en) 1987-09-08 1987-09-08 Wiring layer formed on buried dielectric and manufacture thereof
JP62-225039 1987-09-08

Publications (2)

Publication Number Publication Date
KR890005844A KR890005844A (ko) 1989-05-17
KR940008358B1 true KR940008358B1 (ko) 1994-09-12

Family

ID=16823091

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880003697A Expired - Fee Related KR940008358B1 (ko) 1987-09-08 1988-04-01 매입 유전체상에 형성된 배선층 및 그 제조방법

Country Status (4)

Country Link
US (1) US5041898A (https=)
JP (1) JPS6467945A (https=)
KR (1) KR940008358B1 (https=)
DE (2) DE3844719C2 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516720A (en) * 1994-02-14 1996-05-14 United Microelectronics Corporation Stress relaxation in dielectric before metallization
KR100236097B1 (ko) * 1996-10-30 1999-12-15 김영환 반도체 장치의 격리막 형성방법
US6306727B1 (en) 1997-08-18 2001-10-23 Micron Technology, Inc. Advanced isolation process for large memory arrays
US6451655B1 (en) * 1999-08-26 2002-09-17 Stmicroelectronics S.R.L. Electronic power device monolithically integrated on a semiconductor and comprising a first power region and at least a second region as well as an isolation structure of limited planar dimension
DE10041691A1 (de) 2000-08-24 2002-03-14 Infineon Technologies Ag Halbleiteranordnung
DE10051909B4 (de) * 2000-10-19 2007-03-22 Infineon Technologies Ag Randabschluss für Hochvolt-Halbleiterbauelement und Verfahren zum Herstellen eines Isolationstrenches in einem Halbleiterkörper für solchen Randabschluss
DE10242661A1 (de) * 2002-09-13 2004-03-25 Conti Temic Microelectronic Gmbh Verfahren zum Herstellen von Isolationsstrukturen
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7247570B2 (en) * 2004-08-19 2007-07-24 Micron Technology, Inc. Silicon pillars for vertical transistors
US7285812B2 (en) 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7199419B2 (en) * 2004-12-13 2007-04-03 Micron Technology, Inc. Memory structure for reduced floating body effect
US7229895B2 (en) * 2005-01-14 2007-06-12 Micron Technology, Inc Memory array buried digit line
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
KR100703042B1 (ko) * 2006-09-08 2007-04-09 (주)에이펙스 검사용 프로브 기판 및 그 제조 방법
KR100703043B1 (ko) * 2006-09-21 2007-04-09 (주)에이펙스 검사용 프로브 기판 및 그 제조 방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
IT1397603B1 (it) * 2009-12-21 2013-01-16 St Microelectronics Srl Trincee di isolamento per strati semiconduttori.
US9401363B2 (en) 2011-08-23 2016-07-26 Micron Technology, Inc. Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2949360A1 (de) * 1978-12-08 1980-06-26 Hitachi Ltd Verfahren zur herstellung einer oxidierten isolation fuer integrierte schaltungen
JPS56146247A (en) * 1980-03-25 1981-11-13 Fujitsu Ltd Manufacture of semiconductor device
JPS58105551A (ja) * 1981-11-20 1983-06-23 Fujitsu Ltd 半導体装置
JPS58200554A (ja) * 1982-05-19 1983-11-22 Hitachi Ltd 半導体装置の製造方法
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits
US4819054A (en) * 1982-09-29 1989-04-04 Hitachi, Ltd. Semiconductor IC with dual groove isolation
US4910575A (en) * 1986-06-16 1990-03-20 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and its manufacturing method

Also Published As

Publication number Publication date
DE3844719C2 (de) 1995-06-14
JPS6467945A (en) 1989-03-14
US5041898A (en) 1991-08-20
DE3825547C2 (https=) 1992-12-03
KR890005844A (ko) 1989-05-17
DE3825547A1 (de) 1989-03-16

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