KR940008033A - 집적 회로 디바이스의 활성 회로 영역 상의 와이어 접합 방법 및 집적 회로 디바이스 - Google Patents
집적 회로 디바이스의 활성 회로 영역 상의 와이어 접합 방법 및 집적 회로 디바이스 Download PDFInfo
- Publication number
- KR940008033A KR940008033A KR1019930018082A KR930018082A KR940008033A KR 940008033 A KR940008033 A KR 940008033A KR 1019930018082 A KR1019930018082 A KR 1019930018082A KR 930018082 A KR930018082 A KR 930018082A KR 940008033 A KR940008033 A KR 940008033A
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- South Korea
- Prior art keywords
- polyimide layer
- active circuit
- integrated circuit
- circuit device
- polyimide
- Prior art date
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- 238000000034 method Methods 0.000 title claims 12
- 239000004642 Polyimide Substances 0.000 claims abstract 26
- 229920001721 polyimide Polymers 0.000 claims abstract 26
- 239000000463 material Substances 0.000 claims abstract 4
- 239000004020 conductor Substances 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 2
- 238000005538 encapsulation Methods 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
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Abstract
집적 회로 디바이스(10)의 활성 회로(13)상의 와이어 접합은 활성 회로에 관련하여 상부에 폴리이미드 물질층(23)을 제공하고, 활성 회로에 대향하는 폴리이미드 중 상에 접합 패드를 피착하며, 접합 패드를 활성 회로에 전기적으로 접속하고, 및 와이어(33)을 접합 패드에 접합함으로써 달성된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명이 실시하는 집적 회로 디바이스의 단면도.
제2도는 제1도의 접합 패드의 선택적인 배열을 도시한 단면도.
제3도는 제1도 및 제2도의 와이어 접합을 행하기 위하여 사용된 접합 장치의 일부분인 접합 변환기를 도시한 정면도.
제4도는 제1도 및 제2도의 와이어 접합을 행하기 위하여 사용된 접합 장치의 다이어그램.
Claims (20)
- 집적 회로 디바이스의 활성 회로 상에 와이어 접합을 행하는 방법에 있어서, 활성 영역에 관련하여 폴리이미등 물질 층을 상부에 제공하는 단계, 활성 회로에 대향하는 폴리이미드 층 상에 접합 패드를 피착하는 단계, 폴리이미드 층을 통해 활성 회로에 접합 패드를 전기적으로 접속하는 단계 및, 접합 패드에 와이어를 접합하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 와이어 접합 단계가 최소한 100kHz의 주파수에서 접합 변환기를 조작하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제2항에 있어서, 폴리이미드 층이 6-13GPa 범위 내의 탄성 모듈을 갖는 것을 특징으로 하는 방법.
- 제2항에 있어서, 폴리이미드 층이 3×10-6내지 10×10-6in/in/℃ 범위 내의 열 팽창 계수를 갖는 것을 특징으로 하는 방법.
- 제4항에 잇어서, 폴리이미드 층이 3 내지 6 미크론 범위 내의 두께를 갖고, 약 3의 유전 상수를 갖는 것을 특징으로 하는 방법.
- 제5항에 있어서, 상기 접속 단계가 폴리이미드 층을 통해 연장되는 관통 개구를 폴리이미드 층 내에 제공하는 단계 및 개구를 통해 연장되고 활성 회로와의 전기적인 접속을 종결되는 전기적 도체를 개구에 배치하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제6항에 있어서, 와이어가 금으로 제조되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 접합 단계가 최소한 100kHz의 주파수에서 접합 밴환기를 조작하는 단계를 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 폴리이미드 층이 6-13GPa 범위 내의 탄성 모듈을 갖는 것을 특징으로 하는 방법.
- 제1항에 있어서, 폴리이미드 층이 3×10-6내지 10×10-6in/in/℃ 범위 내의 열 팽창 계수를 갖는 것을 특징으로 하는 방법.
- 제1항에 있어서, 폴리이미드 층이 3 내지 6미크론 범어 내의 두께를 갖고, 약 3의 유전상수를 갖는 것을 특징으로 하는 방법.
- 집적 회로를 제조하는 방법에 있어서, 활성 회로를 제공하는 단계, 활성 회로에 관련하여 폴리이미드 물질 층을 상부에 제공하는 단계, 활성 회로에 대향하는 상기 폴리이미드 층 상에 다수의 접합 패드를 피착하는 단계, 폴리이미드 층을 통해 활성 회로에 전기적으로 접합 패드를 전기적으로 접속하는 단계, 접합 패드에 다수의 와이어를 각각 접합하는 단계, 및 폴리이미드 층, 접합 패드 및 와이어 상의 봉입부를 몰딩하는 단계를 포함하는 것을 특징으로 하는 방법.
- 집적 회로 디바이스에 있어서, 활성 회로, 상기 활성 회로에 관련하여 상부에 배치된 폴리이미드 물질 층, 상기 활성 회로와 상기 접합 패드 사이에 삽입된 폴리이미드 층 상에 피착되고, 상기 폴리이미드 층을 통해 상기 활성 회로에 전기적으로 접속되는 다수의 접합 패드, 및 각 상기 접합 패드를 상기 와이어 리드 구조물에 접속하고 각각의 상기 접합 패드에 접합되는 길게 연장된 접합 연부를 각각 가지는 다수의 와이어를 포함하는 것을 특징으로 하는 집적 회로 디바이스.
- 제13항에 있어서, 상기 폴리이미드 층이 상기 활성 회로를 각각의 접합 패드에 전기적으로 접속하고 상기 관통 개구 내에 각각 제공된 다수의 전기적 도체를 포함하며, 상기 전기적 도체가 각각의 접합 패드에 전기적으로 접속되고 상기 활성 회로와 전기적으로 접촉하는 것을 종결하기 위해 각각의 관통 개구 및 상기 폴리이미드 층, 상기 접합 패드 및 상기 와이어 상에 몰드된 봉입부를 통해 연장되는 것을 특징으로 하는 집적 회로 디바이스.
- 제14항에 있어서, 상기 접합 패드가 각각의 전기적 도체에 대하여 상부에 배치되는 것을 특징으로 하는 집적 회로 디바이스.
- 제15항에 있어서, 상기 접합 패드가 각각의 전기적 도체에 대하여 상부에 놓여지지 않도록 배치된 것을 특징으로 하는 집적 회로 디바이스.
- 제13항에 있어서, 폴리이미드 층이 최소한 6GPa의 탄성 모듈을 갖는 것을 특징으로 하는 집적 회로 디바이스.
- 제13항에 있어서, 폴리이미드 층이 3×10-6내지 10×10-6in/in/℃ 범위 내의 열 팽창 계수를 갖는 것을 특징으로 하는 집접 회로 디바이스.
- 제13항에 있어서, 상기 폴리이미드 층이 3 내지 6 미크론 범위 내의 두께를 갖고, 약 3의 유전 상수를 갖는 것을 특징으로 하는 집적 회로 디바이스.
- 제13항에 있어서, 상기 활성 회로와 상기 폴리이미드 층 사이에 삽입되고 실리콘 질화물 및 실리콘 산화물중 하나로 이루어진 보호성 오버코트 층을 포함하는 것을 특징으로 하는 집적 회로 디바이스.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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US94308792A | 1992-09-10 | 1992-09-10 | |
US07/943,087 | 1992-09-10 |
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KR940008033A true KR940008033A (ko) | 1994-04-28 |
KR100335591B1 KR100335591B1 (ko) | 2002-08-24 |
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KR1019930018082A KR100335591B1 (ko) | 1992-09-10 | 1993-09-09 | 집적회로디바이스의액티브회로영역상의와이어본딩방법및집적회로디바이스 |
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Country | Link |
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EP (1) | EP0587442B1 (ko) |
JP (1) | JPH06204277A (ko) |
KR (1) | KR100335591B1 (ko) |
DE (1) | DE69323515T2 (ko) |
MY (1) | MY110904A (ko) |
SG (1) | SG47534A1 (ko) |
TW (1) | TW253987B (ko) |
Cited By (1)
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US10663175B2 (en) | 2017-05-30 | 2020-05-26 | Samsung Electronics Co., Ltd. | Home appliance |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3420435B2 (ja) | 1996-07-09 | 2003-06-23 | 松下電器産業株式会社 | 基板の製造方法、半導体装置及び半導体装置の製造方法 |
TW445616B (en) | 1998-12-04 | 2001-07-11 | Koninkl Philips Electronics Nv | An integrated circuit device |
US8021976B2 (en) | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US6503820B1 (en) | 1999-10-04 | 2003-01-07 | Koninklijke Philips Electronics N.V. | Die pad crack absorption system and method for integrated circuit chip fabrication |
DE10200932A1 (de) * | 2002-01-12 | 2003-07-24 | Philips Intellectual Property | Diskretes Halbleiterbauelement |
DE10242325A1 (de) * | 2002-09-12 | 2004-04-01 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Halbleiter mit Isolierschicht und Verfahren zu dessen Herstellung |
DE10245867A1 (de) * | 2002-09-30 | 2004-04-15 | Siced Electronics Development Gmbh & Co. Kg | Leistungs-Halbleiterbauelement mit verbesserten Anschlusskontakten und Verfahren zu dessen Herstellung |
CN100449734C (zh) * | 2004-03-16 | 2009-01-07 | 松下电器产业株式会社 | 半导体器件 |
JP4696532B2 (ja) | 2004-05-20 | 2011-06-08 | 株式会社デンソー | パワー複合集積型半導体装置およびその製造方法 |
JP4674522B2 (ja) | 2004-11-11 | 2011-04-20 | 株式会社デンソー | 半導体装置 |
DE102006003930A1 (de) * | 2006-01-26 | 2007-08-09 | Infineon Technologies Austria Ag | Leistungshalbleiterelement mit internen Bonddrahtverbindungen zu einem Bauelementsubstrat und Verfahren zur Herstellung desselben |
JP5732035B2 (ja) * | 2009-03-20 | 2015-06-10 | ミクロガン ゲーエムベーハー | 垂直接触電子部品及びその製造方法 |
JP2015204393A (ja) * | 2014-04-15 | 2015-11-16 | サンケン電気株式会社 | 半導体装置 |
JP6690509B2 (ja) * | 2016-11-22 | 2020-04-28 | 株式会社村田製作所 | 半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US4017886A (en) * | 1972-10-18 | 1977-04-12 | Hitachi, Ltd. | Discrete semiconductor device having polymer resin as insulator and method for making the same |
JPS51118965A (en) * | 1976-02-23 | 1976-10-19 | Hitachi Ltd | Insulation film of semiconductor device |
US4723197A (en) * | 1985-12-16 | 1988-02-02 | National Semiconductor Corporation | Bonding pad interconnection structure |
JPH01103867A (ja) * | 1987-10-16 | 1989-04-20 | Sanyo Electric Co Ltd | トランジスタ |
JP2559602B2 (ja) * | 1987-11-30 | 1996-12-04 | 超音波工業株式会社 | ワイヤボンダ用超音波振動子 |
JP2593965B2 (ja) * | 1991-01-29 | 1997-03-26 | 三菱電機株式会社 | 半導体装置 |
US5201454A (en) * | 1991-09-30 | 1993-04-13 | Texas Instruments Incorporated | Process for enhanced intermetallic growth in IC interconnections |
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1993
- 1993-09-09 KR KR1019930018082A patent/KR100335591B1/ko not_active IP Right Cessation
- 1993-09-10 EP EP93307165A patent/EP0587442B1/en not_active Expired - Lifetime
- 1993-09-10 DE DE69323515T patent/DE69323515T2/de not_active Expired - Fee Related
- 1993-09-10 MY MYPI93001860A patent/MY110904A/en unknown
- 1993-09-10 JP JP5226045A patent/JPH06204277A/ja active Pending
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US10663175B2 (en) | 2017-05-30 | 2020-05-26 | Samsung Electronics Co., Ltd. | Home appliance |
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EP0587442B1 (en) | 1999-02-17 |
EP0587442A2 (en) | 1994-03-16 |
DE69323515D1 (de) | 1999-03-25 |
DE69323515T2 (de) | 1999-06-17 |
JPH06204277A (ja) | 1994-07-22 |
MY110904A (en) | 1999-06-30 |
KR100335591B1 (ko) | 2002-08-24 |
EP0587442A3 (ko) | 1994-08-03 |
SG47534A1 (en) | 1998-04-17 |
TW253987B (ko) | 1995-08-11 |
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