KR940002949A - Etching method of metal wiring contact region of semiconductor device - Google Patents

Etching method of metal wiring contact region of semiconductor device Download PDF

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Publication number
KR940002949A
KR940002949A KR1019920012905A KR920012905A KR940002949A KR 940002949 A KR940002949 A KR 940002949A KR 1019920012905 A KR1019920012905 A KR 1019920012905A KR 920012905 A KR920012905 A KR 920012905A KR 940002949 A KR940002949 A KR 940002949A
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KR
South Korea
Prior art keywords
film
metal wiring
semiconductor device
sog film
etching method
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Application number
KR1019920012905A
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Korean (ko)
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KR100268859B1 (en
Inventor
양대근
Original Assignee
문정환
금성 일렉트론 주식회사
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Priority to KR1019920012905A priority Critical patent/KR100268859B1/en
Publication of KR940002949A publication Critical patent/KR940002949A/en
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Publication of KR100268859B1 publication Critical patent/KR100268859B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 B2O3및 P2O5SOG막을 이용하여 알루미늄 단차를 개선할 수 있는 반도체 장치의 금속배선용 접촉구멍 형성 방법에 관한 것으로, 종래에는 건식 식각시 과대식각 때문에 기판이 손상되고, 알류미늄의 단차가 약화되는 결점이 있었으나, 본 발명에서는 B203및 P2O5SOG막(9,10)을 이용하여 금속배선을 실시할 부위의 식각 기울기를 제어하므로써 상기 결점을 개선시킬 수 있는 것이다.The present invention relates to a method for forming a contact hole for metal wiring of a semiconductor device that can improve the aluminum step by using the B 2 O 3 and P 2 O 5 SOG film, the conventional substrate is damaged due to over-etching during dry etching, aluminum Although the step was weakened, in the present invention, by using the B 2 0 3 and P 2 O 5 SOG film (9,10) to control the etching slope of the site to be subjected to metal wiring can improve the defect will be.

Description

반도체 장치의 금속배선 접촉 영역 식각방법Etching method of metal wiring contact region of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 금속배선 실시할 접촉 영역 식각을 설명하기 위한 공정.2 is a process for explaining the etching of the contact region to be carried out the metallization of the present invention.

Claims (3)

기판(1)위에 산화막(2)을 형성하고 산화막위에 게이트(2)를 패터닝한 후 전표면에 HLD막(8), B2O3SOG막(9)을 P2O5SOG막(10)제거하므로써 접촉영역이 위로 부터 아래로 완만하게 좁아지도록 하는 단계와, 열처리하여 상기 HLD막(8)으로 보론과 인이 확신하므로써 HLD막(8) . B203SOG막(9) 사이에 BPSG막(12)을 형성하고 기판(1) 표면에 유리층(13)을 형성하는 단계와, 플라즈마 평탄화법 또는 식각용액으로 상기 유리층(13)을 제거하고, 막(9,10)을 제거한 후 전표면에 금속을 형성하는 단계를 차례로 실시하여 이루어지는 반도체 장치의 금속배선 접촉영역 식각방법.After the oxide film 2 is formed on the substrate 1 and the gate 2 is patterned on the oxide film, the HLD film 8 and the B 2 O 3 SOG film 9 are formed on the entire surface of the P 2 O 5 SOG film 10. By removing the contact area from the top to the bottom to be gently narrowed, and by heat treatment to ensure the boron and phosphorus to the HLD film (8) HLD film (8). Forming a BPSG film 12 between the B 2 O 3 SOG film 9 and forming a glass layer 13 on the surface of the substrate 1, and using the plasma planarization method or an etching solution to And removing the films (9, 10) and subsequently forming a metal on the entire surface. 제1항에 있어서, B2O3SOG막(9)과 P2O5SOG막(10)을 80℃, 150℃, 200℃에서 각각 1분 동안씩 차례로 열처리하여 형성하는 반도체 장치의 금속배선 접촉영역 식각방법.The metal wiring of the semiconductor device according to claim 1, wherein the B 2 O 3 SOG film 9 and the P 2 O 5 SOG film 10 are formed by sequentially heat treatment for 1 minute at 80 ° C, 150 ° C, and 200 ° C, respectively. Contact area etching method. 제1항에 있어서, 금속으로 Al을 사용하는 반도체 장치의 금속배선 접촉영역 식각방법.The method of claim 1, wherein Al is used as the metal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920012905A 1992-07-20 1992-07-20 Method for forming metal interconnector of semiconductor device KR100268859B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920012905A KR100268859B1 (en) 1992-07-20 1992-07-20 Method for forming metal interconnector of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012905A KR100268859B1 (en) 1992-07-20 1992-07-20 Method for forming metal interconnector of semiconductor device

Publications (2)

Publication Number Publication Date
KR940002949A true KR940002949A (en) 1994-02-19
KR100268859B1 KR100268859B1 (en) 2000-10-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920012905A KR100268859B1 (en) 1992-07-20 1992-07-20 Method for forming metal interconnector of semiconductor device

Country Status (1)

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KR (1) KR100268859B1 (en)

Also Published As

Publication number Publication date
KR100268859B1 (en) 2000-10-16

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