KR970018573A

KR970018573A - Manufacturing Method of Semiconductor Device

Info

Publication number: KR970018573A
Application number: KR1019950031100A
Authority: KR
Inventors: 김범수
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-21
Filing date: 1995-09-21
Publication date: 1997-04-30

Abstract

게이트와 게이트 패턴 사이의 트랜지스터의 활성영역을 전기적으로 접속하기 위한 셀 오픈 패턴(Cell open pattern) 형성시 소자의 포인트 결함을 유발하는 포토레지스트의 미세 유기물질을 제거하는 방법을 개시한다. 본 발명은 포토레지스트 마스크를 이용한 습식 식각공정을 수행하는 경우, O₂플라즈마 식각공정이나, 자외선 베이크(U. V Bake)처리를 수행함으로써, 습식용액(Wet chemical)에 의한 레지스트 패턴의 미세 유기물질의 생성을 억제 또는 제거할 수 있다. 그 결과, 포인트 결함을 감소시킴으로써 소자의 패드간의 브릿지 현상을 방지하여 수율을 향상시킬 수 있다.A method of removing microorganisms in photoresist that causes point defects of a device in forming a cell open pattern for electrically connecting an active region of a transistor between a gate and a gate pattern is disclosed. In the present invention, when performing a wet etching process using a photoresist mask, by performing an O ₂ plasma etching process or an ultraviolet bake (U. V Bake) process, the fine organic material of the resist pattern by a wet solution (Wet chemical) Can inhibit or eliminate the As a result, by reducing the point defects, the bridge phenomenon between the pads of the device can be prevented and the yield can be improved.

Description

Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명의 일 실시예에 의한 셀 오픈 패턴 형성방법을 각 단계별로 순차적으로 도시한 공정단면도.2A through 2F are cross-sectional views sequentially illustrating a method of forming a cell open pattern according to an embodiment of the present invention sequentially in each step.

Claims

Sequentially stacking a first high temperature oxide film, a nitride film, and a second high temperature oxide film on the semiconductor substrate on which the gate pattern is formed to planarize the device; Wet etching the second high temperature oxide film using a photoresist pattern for opening a cell region; O ₂ plasma etching process for removing the fine organic material of the photosensitive film causing a point defect; Dry etching the nitride film and the first high temperature oxide film to expose a predetermined portion of the semiconductor substrate; And a pad forming step for connecting to the opened semiconductor substrate.

The method of claim 1, wherein a 7: 1 BOE (Buffered Oxide Etchant) is used as a chemical solution of the wet etching process.

The method of claim 1, wherein an interlayer insulating film such as Borophoshporus Silic Glass (BPSG), SiN ₄ , p-siH ₄ , and thermal oxide is used in place of the second high temperature oxide film.

Sequentially stacking a first high temperature oxide film, a nitride film, and a second high temperature oxide film on the semiconductor substrate on which the gate pattern is formed to planarize the device; Defining a photosensitive film pattern for defining a cell region of the device; Hardening the photoresist pattern through an ultraviolet bake treatment in order to suppress generation of fine organic materials in the photoresist during wet etching; Wet etching the second high temperature oxide film using a photoresist pattern for opening a cell region; Dry etching the nitride film and the first high temperature oxide film to expose a predetermined portion of the semiconductor substrate; And a pad forming step for connecting to the opened semiconductor substrate.