KR930006835A - Method of forming interlayer insulating film of semiconductor device - Google Patents

Method of forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR930006835A
KR930006835A KR1019910016413A KR910016413A KR930006835A KR 930006835 A KR930006835 A KR 930006835A KR 1019910016413 A KR1019910016413 A KR 1019910016413A KR 910016413 A KR910016413 A KR 910016413A KR 930006835 A KR930006835 A KR 930006835A
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South Korea
Prior art keywords
insulating film
interlayer insulating
forming
semiconductor device
film
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KR1019910016413A
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Korean (ko)
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KR950000854B1 (en
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김창규
최지현
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김광호
삼성전자 주식회사
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Publication of KR930006835A publication Critical patent/KR930006835A/en
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Publication of KR950000854B1 publication Critical patent/KR950000854B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 제조방법에 있어서 층간 절연막 형성방법에 관한 것으로, 소정 영역에 도전층 패턴이 형성된 소정 도전형의 반도체 기판상에 제1층간 절연막과 제2층간 절연막을 순차적으로 형성한 후 상기 기판 상면에 스핀 온 글래스막을 형성하고, 그 다음 상기 도전층 상부의 제1층간 절연막의 표면이 노출될때까지 에치백 공정을 실시한 후 상기 기판상에 잔류된 스핀온 글래스막을 제거하여 상기 제1층간 절연막상에서 제1속도로 성장되고 상기 제2층간 절연막 상에서 상기 제1속도보다 빠른 제2속도로 성장되는 제3층간 절연막을 형성하는 공정을 구비함에 의해 기판내의 접합 파괴없이 우수한 평탄도를 가짐과 동시에 트랜지스터 등의 반도체 소자에 영향을 미치지 않는 층간 절연막의 형성방법을 제공한다.The present invention relates to a method for forming an interlayer insulating film in a method of manufacturing a semiconductor device, wherein the first interlayer insulating film and the second interlayer insulating film are sequentially formed on a predetermined conductive semiconductor substrate having a conductive layer pattern formed in a predetermined region. Forming a spin-on glass film on the upper surface of the substrate, and then performing an etch-back process until the surface of the first interlayer insulating film on the conductive layer is exposed, and then removing the spin-on glass film remaining on the substrate to remove the first interlayer insulating film. Forming a third interlayer insulating film grown at a first rate on the second interlayer insulating film and growing at a second rate faster than the first rate on the second interlayer insulating film to have excellent flatness without breakdown of the junction in the substrate, Provided is a method of forming an interlayer insulating film that does not affect semiconductor elements such as the like.

Description

반도체 장치의 층간 절연막 형성방법Method of forming interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 따른 제조공정도.2 is a manufacturing process diagram according to the present invention.

Claims (8)

소정 도전형의 반도체 기판상의 소정영역에 도전층 패턴이 형성된 반도체 장치의 층간 절연막 형성방법에 있어서, 상기 기판 상부에 제1층간 절연막과 제2층간 절연막을 순차적으로 형성하는 제1공정과, 상기 기판 상면에 절연막을 형성한 후 상기 도전층 상부의 제1층간 절연막의 표면이 노출될때까지 에치백 공정을 실시하는 제2공정과, 상기 제2공정에 의해 기판상에 잔류된 상기 절연막을 제거한 후, 상기 제1층간 절연막상에서 제1속도로 성장되고 상기 제2층간 절연막상에서 상기 제1속도보다 빠른 제2속도로 성장되는 제3층간 절연막을 형성하는 제3공정이 순차적으로 이루어지는 공정을 구비함을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.A method of forming an interlayer insulating film of a semiconductor device, in which a conductive layer pattern is formed in a predetermined region on a predetermined conductive semiconductor substrate, comprising: a first step of sequentially forming a first interlayer insulating film and a second interlayer insulating film on the substrate; After forming an insulating film on the upper surface, the second step of performing an etch back process until the surface of the first interlayer insulating film on the conductive layer is exposed, and after removing the insulating film remaining on the substrate by the second step, And a third step of sequentially forming a third interlayer insulating film grown on the first interlayer insulating film at a first rate and growing at a second rate faster than the first rate on the second interlayer insulating film. An interlayer insulating film forming method of a semiconductor device. 제1항에 있어서, 상기 제1층간 절연막이 고온 산화막 P-TEOS, HTO, O3-TEOS, O3-TEOS등임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of claim 1, wherein the first interlayer insulating film is a high temperature oxide film P-TEOS, HTO, O 3 -TEOS, O 3 -TEOS, or the like. 제2항에 있어서, 상기 제2층간 절연막이 O3-TEOS USG, P-SIH4USG등임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of claim 2, wherein the second insulating interlayer is O 3 -TEOS USG, P-SIH 4 USG, or the like. 제3항에 있어서, 상기 제3층간 절연막이 USG 막임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.4. The method of forming an interlayer insulating film of a semiconductor device according to claim 3, wherein said third interlayer insulating film is a USG film. 제1항에 있어서, 상기 절연막이 스핀-온-글래스막 임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein said insulating film is a spin-on-glass film. 제5항에 있어서, 상기 스핀-온-글래스막이 1000RPM에서 2000RPM정도의 스핀 속도로 도포됨을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of claim 5, wherein the spin-on-glass film is applied at a spin speed of about 1000 RPM to about 2000 RPM. 제1항에 있어서, 상기 제3공정후 소정 온도에서 상기 제3절연막을 열처리하는 공정을 더 구비함을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of claim 1, further comprising heat-treating the third insulating film at a predetermined temperature after the third step. 제7항에 있어서, 상기 열처리가 800℃정도의 온도에서 실시됨을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.8. The method for forming an interlayer insulating film of a semiconductor device according to claim 7, wherein said heat treatment is performed at a temperature of about 800 deg. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910016413A 1991-09-19 1991-09-19 Inter-layer insulating film depositing method KR950000854B1 (en)

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KR1019910016413A KR950000854B1 (en) 1991-09-19 1991-09-19 Inter-layer insulating film depositing method

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Application Number Priority Date Filing Date Title
KR1019910016413A KR950000854B1 (en) 1991-09-19 1991-09-19 Inter-layer insulating film depositing method

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KR950000854B1 KR950000854B1 (en) 1995-02-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990012398A (en) * 1997-07-29 1999-02-25 윤종용 Interlayer insulating film formation method to prevent bit line shift

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990012398A (en) * 1997-07-29 1999-02-25 윤종용 Interlayer insulating film formation method to prevent bit line shift

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KR950000854B1 (en) 1995-02-02

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