KR980005359A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR980005359A
KR980005359A KR1019960022832A KR19960022832A KR980005359A KR 980005359 A KR980005359 A KR 980005359A KR 1019960022832 A KR1019960022832 A KR 1019960022832A KR 19960022832 A KR19960022832 A KR 19960022832A KR 980005359 A KR980005359 A KR 980005359A
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KR
South Korea
Prior art keywords
forming
oxide film
polysilicon layer
semiconductor device
manufacturing
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Application number
KR1019960022832A
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Korean (ko)
Other versions
KR100246777B1 (en
Inventor
박민규
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019960022832A priority Critical patent/KR100246777B1/en
Publication of KR980005359A publication Critical patent/KR980005359A/en
Application granted granted Critical
Publication of KR100246777B1 publication Critical patent/KR100246777B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 폴리실리콘층상에 자연적으로 형성되는 자연산화막을 완전히 제거한 후 텅스텐 실리사이드층을 형성하고, 산화공정 및 열처리공정을 높은온도에서 실시하므로써 폴리실리콘층 및 텅스텐 실리사이드츠에 발생하는 들뜸현상을 억제하여 소자의 신뢰성 및 수율을 향상시킬 수 있는 효과가 있다.SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device, wherein after removing a natural oxide film naturally formed on a polysilicon layer, a tungsten silicide layer is formed and an oxidation process and a heat treatment process are performed at a high temperature. There is an effect to improve the reliability and yield of the device by suppressing the lifting phenomenon generated in the silicides.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a내지 2d 도는 본 발명에 따른 종래 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device according to the present invention.

Claims (4)

반도체 소자의 제조방법에 있어서, 실리콘기판상에 게이트 산화막 및 패터닝된 폴리실리콘층을 형성하는 단계와, 상기 단계로부터 H2O2/NH4+ HNO3+ HF 증기를 이용하여 상기 폴리실리콘층상에 자연적으로 형성된 자연산화막을 제거하는 단계와, 상기단계로부터 상기 폴리실리콘층상에 텅스텐 실리사이드층을 형성한 후 LDD 접합영역을 형성하는 단계와,상기 단계로부터 상기 폴리실리콘층 및 텅스텐 실리사이드층의 측벽에 산화막 스페이서를 형성한 후 고농도불순물 이온을 주입하여 LDD구조를 갖는 접합영역을 형성하는 단계와, 상기 단계로부터 산화공정을 실시하여 상기 실리콘기판의 전체상부면에 산화막을 형성한 후 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, comprising: forming a gate oxide film and a patterned polysilicon layer on a silicon substrate, and using the H 2 O 2 / NH 4 + HNO 3 + HF vapor on the polysilicon layer from the step Removing the naturally formed native oxide film, forming a tungsten silicide layer on the polysilicon layer from the step, and then forming an LDD junction region; and an oxide film on the sidewalls of the polysilicon layer and the tungsten silicide layer Forming a junction region having an LDD structure by implanting high concentration impurity ions after forming a spacer; and performing an oxidation process from the above step to form an oxide film on the entire upper surface of the silicon substrate and then performing a heat treatment process. Method for manufacturing a semiconductor device, characterized in that consisting of. 제 1 항에 있어서, 상기 H2O2/NH4액의 온도는 75 내지 85℃인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the H 2 O 2 / NH 4 liquid has a temperature of 75 to 85 ° C. 7. 제 1 항에 있어서, 상기 산화공정은 950 내지 1000℃의 온도조건에서 20 내지 30분간 실시되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the oxidation process is performed at a temperature of 950 to 1000 ° C. for 20 to 30 minutes. 제 1 항에 있어서, 상기 열처리공정은 N2가스 분위기 및 950 내지 1050℃의 온도조건에서 20 내지 30분간 실시되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the heat treatment is performed for 20 to 30 minutes in an N 2 gas atmosphere and a temperature condition of 950 to 1050 ° C. 3. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960022832A 1996-06-21 1996-06-21 Method of manufacturing semiconductor device KR100246777B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960022832A KR100246777B1 (en) 1996-06-21 1996-06-21 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960022832A KR100246777B1 (en) 1996-06-21 1996-06-21 Method of manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR980005359A true KR980005359A (en) 1998-03-30
KR100246777B1 KR100246777B1 (en) 2000-03-15

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KR1019960022832A KR100246777B1 (en) 1996-06-21 1996-06-21 Method of manufacturing semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100593740B1 (en) * 2004-09-16 2006-06-28 삼성전자주식회사 Method of removing native oxide film

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950021272A (en) * 1993-12-30 1995-07-26 김주용 Transistor manufacturing method of semiconductor device
KR0147417B1 (en) * 1994-06-15 1998-08-01 김주용 Method for removing a etching damage reginon of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100593740B1 (en) * 2004-09-16 2006-06-28 삼성전자주식회사 Method of removing native oxide film

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Publication number Publication date
KR100246777B1 (en) 2000-03-15

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