JP2003069033A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the threshold voltage, and to increase the speed without deteriorating integration even if an SOI substrate is used. SOLUTION: An interval Ds between the source/drain impurity layer 7 and the sapphire substrate 1 is set to approximately 0.1 to 0.2 μm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor device using an SOI substrate.

[0002]

2. Description of the Related Art Conventionally, SOS (Silicon On)
As the MOS structure formed on the Sapphire substrate, there are a structure in which the source / drain impurity layer is completely separated from the sapphire surface and a structure in which the source / drain impurity layer is in close contact with the sapphire surface.

FIG. 3 is a sectional view showing the structure of a conventional MOS transistor formed on an SOS substrate.
3A shows a structure in which the source / drain impurity layer is completely separated from the sapphire surface, and FIG. 3B shows a structure in which the source / drain impurity layer is in close contact with the sapphire surface. Figure 3
In (a), the single crystal silicon layer 12 is formed on the sapphire substrate 11, and the recombination center 19 is formed at the interface between the sapphire substrate 11 and the single crystal silicon layer 12.

A polycrystalline silicon gate 14 is formed on the single crystal silicon layer 12 with a gate insulating film 13 interposed therebetween, and a sidewall 16 is formed on the side wall of the polycrystalline silicon gate 14. In addition, the single crystal silicon layer 1
2, source / drain impurity layers 17 are formed, and LDD regions 15 are formed under the sidewalls 16.
Are formed.

Here, the source / drain impurity layer 17
Are formed so as to be completely separated from the sapphire substrate 11, and the source / drain depletion layer 18 at the interface of the source / drain impurity layer 17 does not reach the sapphire substrate 11. Therefore, in the structure in which the source / drain impurity layer 17 is completely separated from the sapphire substrate 11, the body potential can be fixed, the threshold voltage Vth can be stabilized, and the source / drain drain can be stabilized. It is possible to prevent a decrease in withstand voltage.

On the other hand, in FIG. 3B, a single crystal silicon layer 22 is formed on the sapphire substrate 21, and a recombination center 29 is formed at the interface between the sapphire substrate 21 and the single crystal silicon layer 22. There is. Further, a polycrystalline silicon gate 24 is formed on the single crystal silicon layer 22 via a gate insulating film 23, and sidewalls 26 are formed on the side walls of the polycrystalline silicon gate 24.

A source / drain impurity layer 27 is formed in the single crystal silicon layer 22, and an LDD region 25 is formed below the sidewall 26. Here, the source / drain impurity layer 27 is formed so as to be completely adhered to the sapphire substrate 21, and the source / drain depletion layer 28 at the interface of the source / drain impurity layer 27 is formed at the interface with the sapphire substrate 21. There is no such thing.

Therefore, the source / drain impurity layer 17
However, in the structure in which the sapphire substrate 11 is completely in close contact with the sapphire substrate 11, the junction capacitance becomes small and the speed can be increased.

[0009]

However, as shown in FIG.
In the structure (a) in which the source / drain impurity layer 17 is completely separated from the sapphire substrate 11, the source / drain impurity layer 17 is exposed on the sapphire substrate 11 side,
Since the junction capacitance formed at the interface of the source / drain impurity layer 17 increases, there is a problem that it is disadvantageous in increasing the speed.

Further, in the structure in which the source / drain impurity layer 27 of FIG. 3B is completely adhered to the sapphire substrate 21, the body region is isolated, and the threshold voltage Vth varies due to the accumulation of hot carriers. However, there is a problem that the breakdown voltage between the source / drain is lowered. On the other hand, the source / drain impurity layer 27 is the sapphire substrate 2
Although there is a method of using a body contact technique to stabilize the body potential even when it is in complete contact with No. 1, this method has a problem that the integration degree is deteriorated and the pattern design is complicated. was there.

Therefore, an object of the present invention is to provide a semiconductor device capable of stabilizing the threshold voltage and increasing the speed without deteriorating the degree of integration even when an SOI substrate is used, and its manufacture. Is to provide a method.

[0012]

In order to solve the above problems, according to a semiconductor device of claim 1, an SOI substrate and a gate electrode formed on the SOI substrate via a gate insulating film are provided. A source / depletion layer formed on the single crystal silicon layer of the SOI substrate and formed at an interface with the single crystal silicon layer while reaching a distance from the insulating layer of the SOI substrate to the insulating layer of the SOI substrate; And a drain impurity layer.

As a result, even when the source / drain impurity layer is separated from the insulating layer of the SOI substrate, the depletion layer at the source / drain impurity layer interface is prevented from expanding and is formed at the source / drain impurity layer interface. It is possible to reduce the junction capacitance. On the other hand, since the source / drain impurity layer is separated from the insulating layer of the SOI substrate, it becomes possible to diffuse hot carriers in the body region through the gap between the source / drain impurity layer and the insulating layer of the SOI substrate. With that hot carrier SO
It becomes possible to trap at the recombination center formed at the interface between the insulating layer of the I substrate and the single crystal silicon layer.

Therefore, the body potential can be stabilized without using the body contact technique, and the threshold voltage can be stabilized while maintaining a high degree of integration, and the junction capacitance can be stabilized. It is also possible to reduce speed and increase the speed. According to a second aspect of the semiconductor device, the SOI substrate is an SOS substrate.

As a result, a large number of recombination centers can be formed at the interface between the sapphire layer and the single crystal silicon layer, and hot carriers in the body region can be efficiently trapped. According to a third aspect of the semiconductor device, the distance between the insulating layer of the SOI substrate and the source / drain impurity layer is 0.1 to 0.2 μm.

This allows the depletion layer at the source / drain impurity layer interface to reach the insulating layer of the SOI substrate while keeping the source / drain impurity layer separated from the insulating layer of the SOI substrate. It is possible to suppress the spread of the depletion layer at the interface of the impurity layers, to achieve high speed, to stabilize the threshold voltage and to improve the source / drain breakdown voltage without deteriorating the integration degree. be able to.

Further, according to the method of manufacturing a semiconductor device of claim 4, a step of forming a gate electrode on the SOI substrate via a gate insulating film, and an insulating layer of the SOI substrate using the gate electrode as a mask. The ion implantation of impurities into the single crystal silicon layer of the SOI substrate, and the distance between the insulating layer of the SOI substrate and the ion-implanted impurity layer is 0.1 to 0.2 μm. Thus, a step of performing heat treatment is provided.

As a result, the source / drain impurity layer is changed to the SOI by simply changing the implantation conditions and the heat treatment conditions.
The distance between the insulating layer of the SOI substrate and the source / drain impurity layer can be reduced by keeping the distance from the insulating layer of the substrate, and the MOS structure formed on the SOI substrate can be realized without complicating the manufacturing process. Maintain a high degree of integration, and
It is possible to stabilize the threshold voltage and further increase the speed.

[0019]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a single crystal silicon layer 2 is formed on a sapphire substrate 1, and at the interface between the sapphire substrate 1 and the single crystal silicon layer 2, a difference such as a lattice constant between the sapphire substrate 1 and the single crystal silicon layer 2. Due to, the recombination center 9 is formed.

A polycrystalline silicon gate 4 is formed on the silicon layer 2 via a gate insulating film 3, and a sidewall 6 is formed on the side wall of the polycrystalline silicon gate 4. In the single crystal silicon layer 2, the source /
The drain impurity layer 7 is formed, and the LDD region 5 is formed below the sidewall 6.

Here, the source / drain impurity layer 7 is
It is formed so as to be separated from the sapphire substrate 1 by a predetermined distance Ds, and the predetermined distance Ds is set so that the source / drain depletion layer 8 at the interface of the source / drain impurity layer 7 reaches the sapphire substrate 1. For example, the distance Ds between the source / drain impurity layer 7 and the sapphire substrate 1
Is preferably 0.1 to 0.2 μm.

As a result, the source / drain impurity layer 7
Even when is separated from the sapphire substrate 1, it is possible to suppress the spread of the depletion layer 8 at the interface between the source / drain impurity layers 7 and reduce the junction capacitance formed at the interface between the source / drain impurity layers 7. On the other hand, since the source / drain impurity layer 7 is separated from the sapphire substrate 1, the hot carriers h ^{+ in the} body region pass through the gap between the source / drain impurity layer 7 and the sapphire substrate 1.
Can be diffused and the hot carriers h ⁺ can be trapped in the recombination center 9 formed at the interface between the sapphire substrate 1 and the single crystal silicon layer 2.

Therefore, not only the junction capacitance can be reduced and the speed can be increased, but also the body potential can be stabilized without using the body contact technique, and the high integration can be maintained. At the same time, it is possible to stabilize the threshold voltage and improve the breakdown voltage between the source / drain. As a result, it can be easily applied to a high-speed LSI in a field where the power supply voltage is high.

The polycrystalline silicon gate 4 may be a tungsten silicide gate, a molybdenum silicide gate, or the like, or may have a laminated structure of these. FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention. In FIG. 2A, a single crystal silicon layer 2 is formed on the sapphire substrate 1 by epitaxially growing silicon on the sapphire substrate 1. Here, the thickness T of the single crystal silicon layer 2 is, for example, 0.3.
It can be about μm.

Then, a silicon oxide film is formed on the single crystal silicon layer 2 by thermal oxidation of the single crystal silicon layer 2, and a high concentration n-type polycrystalline silicon layer is formed by a method such as CVD. Then, the silicon oxide film and the polycrystalline silicon layer are patterned by the photolithography technique to form the gate insulating film 3 and the polycrystalline silicon gate 4.

Here, the thickness of the gate insulating film 3 can be set to 100 Å, and the thickness of the polycrystalline silicon gate 4 can be set to 3000 Å, for example. Next, FIG. 2 (b)
As shown in, the LDD region 5 is formed by performing ion implantation IP1 of an n-type impurity such as phosphorus using the polycrystalline silicon gate 4 as a mask. Here, the junction depth X1 of the LDD region 5 can be set to 0.1 μm, for example. As conditions for the ion implantation IP1, for example, phosphorus dose amount is 3E + 13 and energy is 30 Ke.
It can be V.

Next, as shown in FIG. 2C, a silicon oxide film is formed on the entire surface by a method such as CVD, and anisotropic etching such as RIE is performed, so that the sidewalls of the polycrystalline silicon gate 4 are etched. Sidewalls 6 are formed on. Here, the spacer length H of the sidewall 6 is, for example, 0.
It can be about 1 μm. Then, source / drain impurity layer 7 is formed by performing ion implantation IP2 of an n-type impurity such as arsenic using sidewall 6 and polycrystalline silicon gate 4 as a mask. Here, the junction depth X2 of the source / drain impurity layer 7 before the heat treatment can be set to, for example, 0.15 μm.
As conditions for the ion implantation IP2, for example, the dose amount of arsenic can be set to 5E + 15 and the energy can be set to 150 KeV.

Next, as shown in FIG.
By performing heat treatment on the SOS substrate on which the drain impurity layer 7 is formed, the junction depth X3 of the source / drain impurity layer 7 after the heat treatment is set to about 0.2 μm, and the source / drain impurity layer 7 and the sapphire substrate 1 are separated from each other. The interval Ds is 0.
It is about 1 μm. Here, the heat treatment is performed by, for example, RTP (Rapid thermal) such as lamp annealing.
Process) can be used, and the conditions for lamp annealing can be, for example, 1000 ° C. and 30 seconds.

As a result, the distance between the source / drain impurity layer 7 and the sapphire substrate 1 can be narrowed while the source / drain impurity layer 7 remains separated from the sapphire substrate 1 only by heat treatment. Source / drain impurity layer 7 interface / source / drain depletion layer 8
However, it is possible to reach the sapphire substrate 1.

Incidentally, SOI (Silicon On I)
Although the SOS substrate has been described as an example of the substrate, any SOI substrate may be used.
It may be an IMOX substrate or a bonded substrate.

[0031]

As described above, according to the present invention,
By narrowing the distance between the insulating layer of the SOI substrate and the source / drain impurity layer, high integration is maintained,
It is possible to stabilize the threshold voltage, reduce the junction capacitance, and increase the speed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a structure of a MOS transistor formed on a conventional SOS substrate.

[Explanation of symbols]

1 sapphire substrate 2 Single crystal silicon layer 3 Gate insulation film 4 Polycrystalline silicon gate 5 LDD area 6 sidewalls 7 Source / drain impurity layer 8 Source / drain depletion layer 9 Recombination center IP1, IP2 ion implantation

Claims (4)

[Claims] 1. An SOI substrate, a gate electrode formed on the SOI substrate via a gate insulating film, a single crystal silicon layer of the SOI substrate,
A semiconductor device, comprising: a source / drain impurity layer reaching a dielectric layer of a depletion layer formed at an interface with the single crystal silicon layer while being separated from the dielectric layer of the OI substrate. 2. The semiconductor device according to claim 1, wherein the SOI substrate is an SOS substrate. 3. The insulating layer of the SOI substrate and the source /
The semiconductor device according to claim 1 or 2, wherein a distance from the drain impurity layer is 0.1 to 0.2 µm. 4. A step of forming a gate electrode on an SOI substrate via a gate insulating film, and a single crystal silicon layer of the SOI substrate so as not to reach an insulating layer of the SOI substrate by using the gate electrode as a mask. And a step of performing heat treatment so that a distance between the insulating layer of the SOI substrate and the ion-implanted impurity layer is 0.1 to 0.2 μm. Of manufacturing a semiconductor device.