KR19990012398A - Interlayer insulating film formation method to prevent bit line shift - Google Patents
Interlayer insulating film formation method to prevent bit line shift Download PDFInfo
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- KR19990012398A KR19990012398A KR1019970035772A KR19970035772A KR19990012398A KR 19990012398 A KR19990012398 A KR 19990012398A KR 1019970035772 A KR1019970035772 A KR 1019970035772A KR 19970035772 A KR19970035772 A KR 19970035772A KR 19990012398 A KR19990012398 A KR 19990012398A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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Abstract
비트라인 쉬프트 방지를 위한 층간절연막 형성방법에 관하여 개시한다. 본 발명은 비트라인 쉬프트 방지막으로 PEOX막 대신에 NSG(Non-Doped Silicate Glass)막을 사용하여, 상압 CVD에서 비트라인 쉬프트 방지막인 NSG막과 제3 절연막인 BPSG막을 동시에 형성함으로써, 공정의 단순화를 달성하고, 동시에 비트라인 쉬프트 방지막과 제2 절연막과 식각비의 차이를 줄여 비트라인 연결을 위한 콘택홀을 형성할 때에 콘택홀이 변형되는 문제를 개선할 수 있다.A method of forming an interlayer insulating film for preventing bit line shift is disclosed. The present invention uses a non-doped silica glass (NSG) film instead of a PEOX film as a bit line shift prevention film, and simultaneously forms an NSG film as a bit line shift prevention film and a BPSG film as a third insulating film in atmospheric pressure CVD, thereby simplifying the process. At the same time, it is possible to reduce the difference between the bit line shift prevention layer and the second insulating layer and the etching ratio, thereby improving the problem of deforming the contact hole when forming the contact hole for the bit line connection.
Description
본 발명은 반도체 메모리의 제조방법에 관한 것으로, 더욱 상세하게는 비트라인 쉬프트 방지를 위한 층간절연막 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor memory, and more particularly, to a method of forming an interlayer insulating film for preventing bit line shift.
반도체 메모리 중에서 특히 디램(DRAM)에 있어서는 1기가 디램(DRAM)의 개발이 완료되고, 256 메가 디램(DRAM)의 양산이 진행되고 있는 현시점에서, COB(Capacitor Over Bit line) 구조의 커패시터 형성방법은 다소 집적도가 떨어지는 4메가급 또는 16메가 급의 디램(DRAM)의 커패시터 형성방법으로 일반화되어 있다. 이러한 COB 구조의 커패시터를 갖는 디램의 제조방법은, ① 반도체 기판에 소자분리 공정에 의한 필드산화막을 형성하여 활성영역을 정의하는 공정, ② 상기 활성영역에 게이트 전극을 갖는 트랜지스터를 형성하고 제1 절연막을 적층하는 공정, ③ 상기 제1 절연막을 패터닝하여 트랜지스터의 소오스와 연결된 매몰 콘택(Buried Contact)을 형성하는 공정, ④ 상기 매몰 콘택과 연결된 커패시터를 구성하고 제2 절연막을 형성하는 공정, ⑤ 상기 제2 절연막을 패터닝하여 비트라인 형성을 위한 다이렉트 콘택(DC: Direct Contact)을 형성하는 공정, ⑥ 상기 DC를 연결하는 비트라인(Bit line)을 형성하고 제3 절연막을 형성하는 공정 및 ⑦ 상기 트랜지스터의 게이트 전극과 연결된 워드라인(Word Line)을 형성하고 패시베이션(Passivation)막을 형성하는 공정으로 이루어진다.Among the semiconductor memories, particularly in DRAM, development of one gigabyte DRAM has been completed, and mass production of 256 mega DRAM (DRAM) is in progress. Thus, a capacitor formation method of a capacitor over bit line (COB) structure has been developed. It is a generalized method for forming capacitors of 4 or 16 mega DRAMs, which are somewhat less integrated. The method of manufacturing a DRAM having a capacitor having a COB structure includes the steps of: (1) forming a field oxide film on a semiconductor substrate by a device isolation process to define an active region; and (2) forming a transistor having a gate electrode in the active region and forming a first insulating film. (3) forming a buried contact connected to the source of the transistor by patterning the first insulating film, and (4) forming a capacitor connected to the buried contact and forming a second insulating film; 2) forming a direct contact (DC) to form a bit line by patterning the insulating film, ⑥ forming a bit line connecting the DC, and forming a third insulating film; Forming a word line connected to the gate electrode and forming a passivation film.
도 1은 종래 기술에 의한 비트라인 쉬프트 방지를 위한 층간절연막 형성방법을 설명하기 위하여 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming an interlayer insulating film for preventing bit line shift according to the prior art.
도 1을 참조하면, 위에서 설명된 COB구조의 디램의 제조공정 중에서, ⑥ 상기 DC를 연결하는 비트라인(Bit line)을 형성하고 제3 절연막을 형성하는 공정에 해당하는 공정이다. 여기서, 이해를 돕기 위하여, 제1 내지 제3 절연막의 구성은 상술한 COB 구조의 디램 제조공정과 동일한 부재로 설명한다. 상세히 설명하면, 반도체 기판(51)에 제1 절연막(도시 안됨)을 포함하는 하부구조(도시 안됨)가 형성되어 있고, 그 위에 제2 절연막(53)으로서 BPSG(Boron Phosphorus Silicate Glass)막과, 도전물질로 구성된 비트라인 패턴(55)과, PEOX막(57) 및 제3 절연막(59)이 각각 구성되어 있다. 여기서 상기 제3 절연막은 BPSG막으로서, 형성 공정을 보다 구체적으로 설명하면, 상기 비트라인 패턴(55)을 형성한 후, 층간절연막(Inter Layer Dielectric)으로서 PEOX막(57)과, 제3 절연막(59), 예컨대 BPSG막을 퇴적한다. 그리고, 평탄화를 위하여 고온에서 리플로우(Reflow)공정을 진행하게 된다. 이때, 고온에서 녹은 제3 절연막(59)의 평탄화만 이루어지는 것이 아니라, 단차가 형성된 영역에서는 비트라인 패턴(55)도 함께 쉬프트(shift)가 이루어진다. 상술한 쉬프트 된 비트라인 패턴(55)은 후속되는 포토마스킹(photo masking) 공정에서 마진(Margin)이 저하되는 원인이 된다. 즉, 비트라인 패턴(55)에 금속배선을 형성하기 위하여 콘택홀(contact hole)을 형성할 때, 비트라인 패턴(55)이 쉬프트 되어 정확하게 정렬이 되지 않는 문제점이 발생한다. 따라서, 기존의 기술에서는 이러한 문제를 방지하기 위하여, 상기 비트라인 패턴(55)과 제3 절연막(59) 사이에 PEOX막(57)을 추가적으로 구성하여 이를 비트라인 패턴(55)의 쉬프트(shift) 방지 목적으로 활용하고 있다.Referring to FIG. 1, in the process of manufacturing the DRAM having the COB structure described above, ⑥ a process corresponding to forming a bit line connecting the DC and forming a third insulating film. Here, for the sake of understanding, the configuration of the first to third insulating films will be described by the same members as the DRAM manufacturing process of the COB structure described above. In detail, a substructure (not shown) including a first insulating film (not shown) is formed on the semiconductor substrate 51, and a BPSG (Boron Phosphorus Silicate Glass) film is formed thereon as the second insulating film 53, A bit line pattern 55 made of a conductive material, a PEOX film 57 and a third insulating film 59 are formed, respectively. Here, the third insulating film is a BPSG film, and the formation process will be described in more detail. After forming the bit line pattern 55, the PEOX film 57 and the third insulating film (Inter Layer Dielectric) are formed. 59), for example, a BPSG film is deposited. In addition, a reflow process is performed at a high temperature for planarization. In this case, not only the planarization of the third insulating layer 59 melted at a high temperature is performed, but also the bit line pattern 55 is shifted together in the stepped region. The shifted bit line pattern 55 causes a margin to decrease in a subsequent photo masking process. That is, when forming a contact hole in order to form a metal wiring in the bit line pattern 55, the bit line pattern 55 is shifted, so that the alignment is not accurately aligned. Accordingly, in the related art, in order to prevent such a problem, a PEOX film 57 is additionally formed between the bit line pattern 55 and the third insulating film 59 to shift the bit line pattern 55. It is used for prevention purposes.
그러나, 상술한 종래 기술에 있어서의 문제점은 다음과 같다. 첫째, PEOX막(57)과, 제3 절연막(59)막을 형성하기 위해서는 먼저 플라즈마 화학 기상 증착(CVD: Chemical Vapor Deposition, 이하 'CVD'라 칭함) 장비에서 PEOX막(57)을 형성하고, 웨이퍼를 다시 상압(Atmosphere Press) CVD 장비로 옮겨서 제3 절연막(59)을 형성해야 하는 번거로움이 있다. 둘째, 후속되는 인터 커넥션(Interconnection) 공정에서 비트라인 패턴(55)을 연결하기 위한 콘택홀을 형성할 때, 상기 PEOX막(57)과 제3 절연막(59)과 식각비(Etching Rate) 차이에 의하여 식각공정에서 콘택홀의 형상이 변형(deform)되는 문제점이 발생한다.However, the problem in the above-mentioned prior art is as follows. First, in order to form the PEOX film 57 and the third insulating film 59, the PEOX film 57 is first formed in a Chemical Vapor Deposition (CVD) apparatus. Is moved to the Atmosphere Press CVD equipment to form the third insulating film 59. Second, when forming a contact hole for connecting the bit line pattern 55 in a subsequent interconnection process, the etching rate is different from that of the PEOX layer 57 and the third insulating layer 59. This causes a problem in that the shape of the contact hole is deformed in the etching process.
본 발명이 이루고자 하는 기술적 과제는 상술한 비트라인 쉬프트 방지용으로 사용되는 PEOX막질을 NSG(Non-Doped Silicate Glass)막질로 대체하여, 상압 CVD에서 비트라인 쉬프트 방지막과 제3 절연막을 동시에 형성함으로써, 공정의 단순화를 달성하고, 동시에 비트라인 쉬프트 방지막과 제3 절연막과 식각비의 차이를 줄여 비트라인 연결을 위한 콘택홀을 형성할 때에 변형을 억제할 수 있는 비트라인 쉬프트 방지를 위한 층간절연막 형성방법을 제공하는데 있다.The technical problem to be achieved by the present invention is to replace the above-described PEOX film quality used for bit line shift prevention with NSG (Non-Doped Silicate Glass) quality, thereby forming a bit line shift prevention film and a third insulating film at the same time in atmospheric pressure CVD, A method of forming an interlayer insulating film for preventing bit line shift can be achieved by reducing the difference between the bit line shift preventing film and the third insulating film and simultaneously reducing the etch ratio to form contact holes for bit line connection. To provide.
도 1은 종래 기술에 의한 비트라인 쉬프트 방지를 위한 층간절연막 형성방법을 설명하기 위하여 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming an interlayer insulating film for preventing bit line shift according to the prior art.
도 2는 본 발명의 실시예에 의한 비트라인 쉬프트 방지를 위한 층간절연막 형성방법을 설명하기 위하여 도시한 단면도이다.2 is a cross-sectional view illustrating a method of forming an interlayer dielectric film for preventing bit line shift according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 간단한 설명 *Brief description of symbols for the main parts of the drawings
100: 반도체 기판, 102: 제2 절연막,100: semiconductor substrate, 102: second insulating film,
104: 비트라인 패턴, 106: 비트라인 쉬프트 방지막,104: bit line pattern, 106: bit line shift prevention film,
108: 제3 절연막.108: third insulating film.
상기의 기술적 과제를 달성하기 위하여 본 발명은, 제1 절연막을 포함하는 하부구조가 형성된 반도체 기판에 제2 절연막을 형성하는 단계와, 상기 제2 절연막을 패터닝하여 비트라인 형성을 위한 콘택홀을 형성하는 단계와, 상기 콘택홀이 형성된 제2 절연막 위에 도전물질을 이용하여 비트라인 패턴을 형성하는 단계와, 상기 비트라인 패턴 위에 비트라인 쉬프트 방지막을 형성하는 단계와, 상기 비트라인 쉬프트 방지막 위에 제3 절연막을 형성하는 단계를 포함하는 비트라인 쉬프트 방지를 위한 층간절연막 형성방법에 있어서, 상기 비트라인 쉬프트 방지막과, 상기 제3 절연막은 동일 장비에서 형성하는 것을 특징으로 하는 비트라인 쉬프트 방지를 위한 층간절연막 형성방법을 제공한다.According to an aspect of the present invention, a second insulating film is formed on a semiconductor substrate on which a lower structure including a first insulating film is formed, and the second insulating film is patterned to form contact holes for forming bit lines. Forming a bit line pattern using a conductive material on the second insulating layer on which the contact hole is formed, forming a bit line shift prevention layer on the bit line pattern, and forming a third line on the bit line shift prevention layer An interlayer insulating film forming method for preventing bit line shift, comprising forming an insulating film, wherein the bit line shift preventing film and the third insulating film are formed in the same equipment. It provides a formation method.
본 발명의 바람직한 실시예에 의하면, 상기 제2 및 제3 절연막은 BPSG를 사용하여 형성하고, 비트라인 패턴은 폴리사이드(polycide)를 사용하여 형성하는 것이 적합하다.According to a preferred embodiment of the present invention, it is preferable that the second and third insulating films are formed using BPSG, and the bit line pattern is formed using polycide.
바람직하게는, 상기 비트라인 쉬프트 방지막과, 제3 절연막이 형성되는 동일 장비는 상압 CVD 장비이고, 비트라인 쉬프트 방지막은 TEOS를 반응소스로 사용하여 형성한 NSG막인 것이 적합하다.Preferably, the same equipment on which the bit line shift prevention film and the third insulating film are formed is an atmospheric pressure CVD device, and the bit line shift prevention film is an NSG film formed using TEOS as a reaction source.
상기 NSG막으로 이루어진 비트라인 쉬프트 방지막은 제3 절연막보다 두께를 얇게 형성하는 것이 바람직하다.The bit line shift preventing film made of the NSG film is preferably thinner than the third insulating film.
본 발명에 따르면, NSG(Non-Doped Silicate Glass)막을 비트라인 쉬프트 방지막으로 사용하여, 상압 CVD에서 비트라인 쉬프트 방지막과 제3 절연막을 동시에 형성함으로써, 공정의 단순화를 달성하고, 동시에 비트라인 쉬프트 방지막과 제3 절연막과 식각비의 차이를 줄여 후속되는 비트라인 연결을 위한 콘택홀을 형성할 때에 변형을 억제할 수 있다.According to the present invention, by using a non-doped silica glass (NSG) film as a bit line shift prevention film and simultaneously forming a bit line shift prevention film and a third insulating film in atmospheric pressure CVD, the process is simplified and at the same time, the bit line shift prevention film is achieved. By reducing the difference between the third insulating layer and the etching ratio, deformation can be suppressed when forming a contact hole for subsequent bit line connection.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시예에 의한 비트라인 쉬프트 방지를 위한 층간절연막 형성방법을 설명하기 위하여 도시한 단면도이다.2 is a cross-sectional view illustrating a method of forming an interlayer dielectric film for preventing bit line shift according to an embodiment of the present invention.
도 2를 참조하면, 트랜지스터와 제1 절연막(도시 안됨)같은 하부구조가 형성된 반도체 기판(100)상에 BPSG를 사용하여 제2 절연막(102)을 형성하고, 리플로우(reflow)공정을 진행하여 평탄화를 완료한다. 상기 제2 절연막(102)에 사진 및 식각공정을 진행하여 비트라인 형성을 위한 다이렉트 콘택홀을 패터닝 한다. 이어서, 상기 콘택홀이 형성된 결과물 상에 불순물이 도핑된 폴리실리콘을 적층하고, 상기 폴리실리콘의 상부에 금속층을 적층하여 열처리를 실시하여 금속실리사이드층을 형성한다. 따라서 비트라인 라인 형성을 위한 도전물질은 폴리사이드 구조를 갖게 된다. 상기 폴리사이드(polycide) 위에 포토레지스트를 도포하고 사진 및 식각공정을 진행하여 비트라인 패턴(104)을 형성한다. 계속해서, 상기 비트라인 패턴(104)이 형성된 웨이퍼를 상압 CVD 장비에서 제3 절연막(108)인 BPSG막을 퇴적하기 전에 TEOS(Tera- Ethyl-Otho-Silicide)를 반응소스로 이용하여 인젝션 헤드(Injection head)로 공급하여 NSG막(Non-doped Silicate Glass)을 먼저 얇게 퇴적함으로써, 비트라인 쉬프트 방지막(106)을 형성한다. 이어서 반응소스로 보론(Boron), 인(Phosphorus) 및 TEOS를 반응소스로 BPSG막을 퇴적함으로써 제3 절연막(108)을 상기 비트라인 쉬프트 방지막(106)보다 두껍게 형성한다. 따라서, 종래에는 장비를 플라즈마 CVD장비와 상압 CVD 장비에서 PEOX막과 BPSG막을 각각 형성하여 공정이 번거로웠으나, 본 발명에서는 이것을 상압 CVD 장비에서만 비트라인 쉬프트 방지막으로서 NSG막과, 제3 절연막(108)으로서의 BPSG막을 동시에 형성함으로써 공정을 단순화시킬 수 있다. 또한, 상기 NSG막은 종래에 기술에서 사용하던 PEOX막보다 BPSG막에 대하여 식각비의 차이가 작아서 후속되는 인터컨넥션 공정(interconnection process)에서 비트라인을 연결하기 위한 콘택홀을 형성할 때에도 콘택홀의 모양이 변형되는 문제를 향상할 수 있다.Referring to FIG. 2, a second insulating film 102 is formed using BPSG on a semiconductor substrate 100 on which a substructure such as a transistor and a first insulating film (not shown) are formed, and a reflow process is performed. Complete the planarization. A photo contact and an etching process are performed on the second insulating layer 102 to pattern a direct contact hole for forming a bit line. Subsequently, polysilicon doped with impurities is laminated on the resultant on which the contact hole is formed, and a metal layer is laminated on the polysilicon to perform heat treatment to form a metal silicide layer. Therefore, the conductive material for forming the bit line lines has a polyside structure. A photoresist is applied on the polycide, and a bit line pattern 104 is formed by performing a photo and etching process. Subsequently, an injection head using TEOS (Tera-Ethyl-Otho-Silicide) as a reaction source before depositing the wafer on which the bit line pattern 104 is formed is a BPSG film, which is the third insulating film 108, in an atmospheric pressure CVD apparatus. The bit line shift prevention film 106 is formed by supplying a NSG film (Non-doped Silicate Glass) thinly by supplying it to the head first. Subsequently, a third insulating film 108 is formed thicker than the bit line shift prevention film 106 by depositing BPSG films using boron, phosphorus and TEOS as reaction sources. Therefore, in the related art, the process was cumbersome by forming the PEOX film and the BPSG film in the plasma CVD equipment and the atmospheric pressure CVD equipment, respectively. By simultaneously forming a BPSG film as), the process can be simplified. In addition, the NSG film has a smaller etch rate difference than that of the PEOX film used in the related art, so that the shape of the contact hole may be changed even when a contact hole for connecting a bit line is formed in a subsequent interconnection process. The problem of deformation can be improved.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 본 발명에 의한 NSG(Non-Doped Silicate Glass)막을 비트라인 쉬프트 방지막으로 사용하면, 첫째, 상압 CVD에서 비트라인 쉬프트 방지막과 제3 절연막을 동시에 형성함으로써 공정의 단순화를 달성하고, 둘째, 비트라인 쉬프트 방지막과 제3 절연막과 식각비의 차이를 줄여 후속되는 비트라인 연결을 위한 콘택홀을 형성할 때에 콘택홀이 변형되는 문제를 개선할 수 있다.Therefore, when the non-doped silica glass (NSG) film according to the present invention is used as the bit line shift prevention film, firstly, the process simplification is achieved by simultaneously forming the bit line shift prevention film and the third insulating film in atmospheric pressure CVD, and secondly, the bit By reducing the difference between the line shift prevention layer and the third insulating layer, an etching ratio may be improved when forming a contact hole for subsequent bit line connection.
Claims (7)
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| KR1019970035772A KR19990012398A (en) | 1997-07-29 | 1997-07-29 | Interlayer insulating film formation method to prevent bit line shift |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930006835A (en) * | 1991-09-19 | 1993-04-22 | 김광호 | Method of forming interlayer insulating film of semiconductor device |
| JPH05259297A (en) * | 1992-03-09 | 1993-10-08 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH06163723A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Semiconductor device and its production |
| JPH0878521A (en) * | 1994-09-01 | 1996-03-22 | Nippon Semiconductor Kk | Fabrication of semiconductor device |
| KR19980030941A (en) * | 1996-10-30 | 1998-07-25 | 김영환 | Semiconductor device manufacturing method |
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1997
- 1997-07-29 KR KR1019970035772A patent/KR19990012398A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930006835A (en) * | 1991-09-19 | 1993-04-22 | 김광호 | Method of forming interlayer insulating film of semiconductor device |
| JPH05259297A (en) * | 1992-03-09 | 1993-10-08 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH06163723A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Semiconductor device and its production |
| JPH0878521A (en) * | 1994-09-01 | 1996-03-22 | Nippon Semiconductor Kk | Fabrication of semiconductor device |
| KR19980030941A (en) * | 1996-10-30 | 1998-07-25 | 김영환 | Semiconductor device manufacturing method |
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