JPH0567732A - Semiconductor element manufacturing method - Google Patents

Abstract

PURPOSE:To provide a semiconductor element manufacturing method capable of enlarging a margin of capacitor capacitance. CONSTITUTION:After an oxide film 6 is formed by a normal pressure CVD method using silane on a word line 4, ozone and organic silane is acted each other by the normal pressure CVD method to accumulate an oxide film 7 having the coarse surface and open a cell contact hole. Thereafter, a polycrystalline silicon 8 is accumulated to form a capacitor storage node having a large surface area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element manufacturing method capable of increasing the surface area of a capacitor in a semiconductor element and manufacturing a semiconductor element aiming to increase the margin of the capacitance of the capacitor.

[0002]

2. Description of the Related Art FIGS. 3 (a) to 3 (c) are cross-sectional views of a prior stage of a conventional semiconductor device manufacturing method.
4C is a process sectional view of the subsequent stage. First, FIG. 3A shows a DRAM (Dynamic Random Access Memory).
LDD (Lightly DopedDrain) in the process of creating
FIG. 6 is a cross-sectional view of a memory cell portion after a transistor having a structure is formed.

In FIG. 3A, reference numeral 21 is a silicon single crystal substrate, and 22 is a field oxide film having a thickness of about 5000 Å for element isolation. Reference numeral 23 is a gate oxide film having a thickness of about 200Å formed by dry oxidation. 3000 in which phosphorus as an impurity is diffused on the gate oxide film 23.
Word line 24 made of polycrystalline silicon with a thickness of about Å
Are formed. Reference numeral 25 is a sidewall oxide film for forming a transistor having an LDD structure.

Next, as shown in FIG.
Atmospheric pressure chemical vapor deposition using silane and oxygen (Chem
The silicon oxide film 26 is deposited by 3000 Å by ical vapor deposition (hereinafter referred to as CVD). Then
As shown in FIG. 3C, a contact hole is opened when the cell capacitor is formed.

Next, the subsequent steps of FIGS. 4 (a) to 4 (c) are entered, and as shown in FIG. 4 (a), polycrystalline silicon is deposited to 2000 liters by a low pressure CVD method using silane. , Capacitor storage node 27 after phosphorus diffusion
As patterning.

Next, as shown in FIG. 4B, the silicon nitride film of the dielectric film 28 is deposited by 100 Å by the low pressure CVD method, and then the polycrystalline silicon 29 is deposited by 2500 Å thereon.
Apply phosphorus diffusion. Then, patterning is performed to form a capacitor.

Next, as shown in FIG. 4C, an interlayer insulating film BPSG30 (Boron-Phospho-Silicate-Glass) is formed.
) Is deposited by the atmospheric pressure CVD method at 6000 Å, and heat treatment is performed at 950 ° C. to perform planarization by reflow.

Next, a bit line contact is opened and wiring is performed with an aluminum alloy 31. Finally, a silicon nitride film 32, which is a passivation film, is formed by plasma CVD to a thickness of 8000Å.

[0009]

However, in the above-described method for manufacturing a DRAM stack capacitor, it has become difficult to secure the required capacity of the memory capacitor due to miniaturization. A thin film of a nitride film, which is a dielectric, has been thinned to increase the capacitance of the capacitor, but there is a problem of leak current, and the increase in capacitance due to the thinning is near the limit.

The present invention provides a method of manufacturing a semiconductor device, which solves the problem of the above-mentioned conventional technique that it is difficult to secure a necessary memory capacitor capacity due to miniaturization.

[0011]

According to the present invention, in a method of manufacturing a semiconductor device, O ₃ and TEOS (tetrae) are formed under a normal pressure under a polycrystalline silicon film to be a capacitor storage node.
Thlorth silicate) is reacted by a CVD method to form a rough insulating film.

[0012]

According to the present invention, since the steps as described above are introduced in the method of manufacturing a semiconductor device, the surface area of polycrystalline silicon deposited on the insulating film having a rough surface is increased, and the capacitance of the storage node is increased. Therefore, the above problems can be eliminated.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. 1 (a) to 1
FIG. 2C is a process sectional view of the first stage of the embodiment, and FIG.
2A to 2C are process cross-sectional views of the subsequent stage.

First, FIG. 1A is a cross-sectional view of a memory cell portion after an LDD transistor is formed in a stack capacitor type DRAM fabrication process. 1 in FIG. 1A is a silicon single crystal substrate as a semiconductor substrate, and 2
Is a field oxide film with a thickness of about 5000 Å for element isolation formed on the silicon single crystal substrate 1, 3 is a gate oxide film with a thickness of about 200 Å by dry oxidation, and 4 is a phosphorus-diffused thickness of about 3000 Å. Crystalline silicon 300
It is a 0Å word line. Reference numeral 5 is a gate sidewall oxide film for forming a transistor having an LDD structure.

Next, as shown in FIG. 1 (b), an oxide film 6 of 2000 Å is deposited on the memory cell portion having such a structure by atmospheric pressure CVD method using silane and oxygen at about 400 ° C. The atmospheric pressure CVD oxide film made of silane is used here because it is a base insulating film that is convenient for forming a rough surface oxide film to be deposited next.

Next, as shown in FIG. 1C, ozone and TEOS are reacted by an atmospheric pressure CVD method to form a rough surface oxide film 7. In forming this rough surface oxide film 7, it is necessary to supply a deposition temperature of about 350 ° C. to 450 ° C. and supply ozone in a sufficient amount for the reaction with TEOS.

Next, as shown in FIG. 2 (a), after the contact hole of the cell capacitor is opened, the low pressure CVD is performed on the entire surface as shown in FIG. 2 (a).
2000 liters of polycrystalline silicon 8 is deposited by the method, and phosphorus diffusion is performed.

Next, as shown in FIG. 2B, after patterning the storage node, a silicon nitride film to be the dielectric 9 is deposited to a thickness of about 100 Å. Then, 2500 Å of polycrystalline silicon 10 to be the upper electrode is deposited, phosphorus is diffused, and then patterned to form a capacitor.

Next, as shown in FIG. 2 (c), the normal pressure CV
The BPSG film 11 is deposited by the D method and reflowed at 950 ° C. to flatten it. Then, a bit line contact is opened to form an aluminum alloy wiring 12, and finally a silicon nitride film 13 which is a passivation film is deposited by 8000 Å by a plasma CVD method.

[0020]

As described above in detail, according to the present invention, the insulating film under the storage node of the capacitor is formed by using the ozone of normal pressure and the rough oxide film of TEOS by the CVD method. It is expected that the surface area of the storage node will increase and the capacity margin of the capacitor will increase.

[Brief description of drawings]

FIG. 1 is a process sectional view of a preceding stage for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a process sectional view of the latter stage of the embodiment.

FIG. 3 is a process sectional view of a former stage of a conventional semiconductor device manufacturing method.

FIG. 4 is a process sectional view of a latter stage of a conventional semiconductor element manufacturing method.

[Explanation of symbols]

 1 Silicon Single Crystal Substrate 2 Field Oxide Film 3 Gate Oxide Film 4 Wordline 5 Gate Sidewall Oxide Film 6 Oxide Film 7 Rough Surface Oxide Film 8 Polycrystalline Silicon 9 Dielectric 10 Polycrystalline Silicon 11 BPSG Film 12 Aluminum Alloy Wiring 13 Silicon Nitride film

Claims (1)

[Claims] 1. A step of depositing an oxide film by a normal pressure CVD method using silane on a semiconductor substrate having a conductive layer on at least a part of its surface, and ozone and organic silane on the oxide film under normal pressure. A step of reacting by a CVD method to deposit a rough surface oxide film; and after forming a cell contact hole in the oxide film and the rough surface oxide film on the conductive layer, a rough surface oxidation including the cell contact hole opening portion A method of manufacturing a semiconductor device, comprising the steps of depositing polycrystalline silicon on a film to form a capacitor storage node.