JP2001053250A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of a capacitor insulation film of high uniformity even in a deep hole of a high aspect ratio by specifying a film thickness of a metal oxide compound film of high dielectric constant. SOLUTION: After a lover electrode 43 of a solid structure is formed, a film-like or island-like first metallic oxide is formed. Thereafter, the first metallic oxide is crystallized and a second metallic oxide of the same composition is further formed on the first metallic oxide. A capacitor insulation film 44 consisting of a polycrystalline tantalum oxide film with a two-layer structure of an upper layer and a lower layer and a silicon nitride film is formed in this way. Since the polycrystalline tantalum oxide film 44 is formed in a hot wall CVD device by making a substrate temperature low, the film thickness in an upper and bottom parts of a deep hole 42 is formed uniform and the film thickness is 7 to 4 nm and film thickness distribution is formed within 20%. Thereby, it is possible to form a polycrystalline tantalum oxide film uniform and to improve reliability by enlarging a capacity value of a DRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a DRAM (Dynamic Random Access Memory).
The present invention relates to a technology that is effective when applied to a semiconductor device having an access memory.

[0002]

2. Description of the Related Art As described in, for example, Japanese Patent Application Laid-Open No. H11-26712, there is known a DRAM having a capacitor over bit line structure in which an information storage capacitor is arranged above a bit line. Have been. This publication discloses a cylindrical lower electrode formed in a deep groove (hole) and a capacitor insulating film formed on the lower electrode as a capacitor (information storage capacitance element) for storing information as electric charge. And an upper electrode. The lower electrode is made of a polycrystalline silicon film, the capacitor insulating film is made of a polycrystalline tantalum oxide film, and the upper electrode is made of a titanium nitride film.
In general, even if the element is miniaturized, a storage capacitance value equal to or higher than a certain value is required regardless of the element size from the viewpoint of maintaining and improving the operational reliability such as anti-α rays. In such a capacitor as described above, the surface area of the electrode is increased by forming the lower electrode into a cylindrical shape in a deep groove, thereby coping with a decrease in the occupied area due to miniaturization of the element.

[0003] For example, on November 10, 1996
Published by the Japan Society of Applied Physics, “Applied Physics” Vol. 65, No. 11
No. pp. 1106 to 1113, the surface of the silicon, which is the lower electrode, is roughened by forming fine irregularities, and the surface area is substantially increased without increasing the planar lower electrode dimension. A technology that can perform such a process, that is, a technology of a so-called HSG (Hemispherical Silicon Grain) structure has been proposed.

[0004]

The above-mentioned deep hole, that is, a capacitor having a three-dimensional structure is a semiconductor memory device (DRAM).
This is effective as one of means for securing the operation reliability as described above, that is, a means for securing a capacitance value equal to or more than a certain value. However, as the generation of the semiconductor device advances and the miniaturization further progresses, the opening diameter of the hole is inevitably small, and the depth of the hole is inevitably increased. In order to form a capacitor in a hole, it is necessary to uniformly form a capacitor insulating film in the hole. However, as described above, a capacitor insulating film is formed in a hole having a narrow opening and a large depth. It is difficult to form uniformly. That is, in order to form a film as uniform as possible even in such a deep hole, a CVD method which is a film forming method excellent in step coverage is used. However, if the hole diameter becomes smaller and the hole depth becomes deeper, the source gas supplied from the hole opening is not sufficiently supplied to the hole bottom, and the film thickness at the hole bottom is smaller than the film thickness at the hole upper portion. It is formed thin. When the above-described tantalum oxide film is used for a capacitor insulating film, for example, pentaethoxy tantalum (T
a) (OC ₂ H ₅ ) ₅ ) is vaporized by a vaporizer, and the substrate temperature is set to about 450 ° C. and the atmospheric pressure is set to 0.5.
The tantalum oxide film is formed by introducing into a reaction chamber maintained at a pressure of about Torr and simultaneously reacting with oxygen (O ₂ ) to be introduced. In the case of such a tantalum oxide film, if a deep hole having a size balance (an aspect ratio of 3 or more) with an opening size of 0.3 μm or less and a depth exceeding 1.0 μm is formed, the thickness of the bottom portion is It has been clarified by the study of the present inventors that the thickness becomes significantly smaller than the film thickness at the upper portion of the hole. Note that such a situation is not limited to the deep hole type lower electrode structure, and the same applies to the simple stack type lower electrode structure. In this specification, a lower electrode having a three-dimensional structure includes both a deep hole type and a stack type.

As described above, when a thick region and a thin region are mixed in the film thickness of the capacitor insulating film, the capacitance value of the capacitor is reduced in the thick film region, and the thin film passes through the capacitor insulating film in the thin film region. This leads to an increase in leakage current.

[0006] Such an increase in the film thickness distribution (a decrease in the film thickness uniformity) is particularly prominent when the capacitor lower electrode is roughened to provide irregularities.

An object of the present invention is to provide a technique capable of forming a highly uniform capacitor insulating film even in a deep hole having an aspect ratio as high as, for example, 3 or more.

Another object of the present invention is to provide a technique capable of forming a highly uniform capacitor insulating film even when a lower electrode having an uneven surface is formed in a deep hole. .

It is a further object of the present invention to provide a technique that can easily secure the capacitance value of a capacitor, has high reliability, and is advantageous in reducing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the semiconductor device of the present invention, the thickness of the metal oxide compound film having a high dielectric constant contained in the capacitor insulating film of the information storage capacitor element (capacitor) may be set to any value between the electrodes constituting the capacitor. 4 nm to 7 nm in the region
Or a film thickness distribution within 20%.

According to such a semiconductor device, since the thickness of the metal oxide compound film having a high dielectric constant is within the range of 4 nm to 7 nm or the thickness distribution is within 20%, the capacitance value of the capacitor is increased. In addition, a highly reliable capacitor can be configured. That is, in a region where the thickness of the capacitor insulating film is 7 nm or more, the effective thickness of the capacitor insulating film is large, which causes a reduction in the capacitance value. On the other hand, in the region where the thickness of the capacitor insulating film is 4 nm or less, the leak current between the capacitor electrodes increases. That is, the characteristics of the entire capacitor reflect the characteristics of each of these regions, resulting in a capacitor having a small capacitance value and a large leak current. In the semiconductor device of the present invention, since such a region having a large film thickness and a region having a small film thickness do not coexist, the characteristics of the capacitor can be a large capacitance value and a small leakage current. Thereby, it is possible to cope with miniaturization of the DRAM, and it is possible to improve the characteristics of a semiconductor device including the DRAM by improving the refresh characteristics.

The crystallized tantalum oxide film can be exemplified as the metal oxide compound film. The tantalum oxide film can be formed uniformly using a hot wall type CVD method described later, and since it has a crystal structure, the relative dielectric constant can be increased and the effective film thickness of the capacitor insulating film can be reduced.

The crystallized tantalum oxide film comprises a first tantalum oxide film on the lower electrode (first electrode) side and an upper electrode (second electrode).
It may have a two-layer structure with the second tantalum oxide film on the (electrode) side. At this time, it is preferable that the thickness of the first tantalum oxide film is less than half of the total thickness of the crystallized tantalum oxide film.

By thus forming the crystallized tantalum oxide film into a two-layer structure, it is possible to reduce the leak current passing through the crystallized tantalum oxide film. That is, since the crystallized tantalum oxide film is constituted in a polycrystalline state, crystal grain boundaries exist,
This crystal grain boundary may act as a path for leakage current. In this regard, if the crystallized tantalum oxide film has a two-layer structure, no crystal grain boundary penetrating the film is formed, and either the first or second tantalum oxide film separates the other crystal grain boundary. Becomes That is, a crystal grain boundary penetrating through the crystallized tantalum oxide film is not formed, and the leakage current path can be cut off. Therefore, the leakage current between the capacitor insulating films can be reduced.

Further, if the thickness of the first tantalum oxide film is reduced, the heat load of the heat treatment for crystallizing the first tantalum oxide film can be reduced, and the reliability of the semiconductor device can be maintained high.

The capacitor insulating film includes a silicon oxynitride film formed in contact with the lower electrode (first electrode). This silicon oxynitride film is formed by forming a silicon nitride film on the lower electrode surface and performing an oxidizing heat treatment for recovering oxygen defects of a metal oxide film (for example, a tantalum oxide film) formed on the silicon nitride film. This is a film formed by oxidizing a silicon nitride film. The silicon nitride film functions as a film for preventing oxidation of the lower electrode during the oxidation heat treatment.

The lower electrode (first electrode) is made of polycrystalline silicon having a roughened surface, a metal or a metal compound. The effect is great when the present invention is applied on such a roughened lower electrode.

(2) The method of manufacturing a semiconductor device according to the present invention comprises:
A metal oxide film that functions as a part of the capacitor insulating film,
In any region of the lower electrode (first electrode) formed as a three-dimensional structure, the film thickness is formed in a range of 4 nm to 7 nm, or the film thickness distribution is formed within 20%.

Further, the method of manufacturing a semiconductor device according to the present invention
After forming a lower electrode (first electrode) having a three-dimensional structure, a film-shaped or island-shaped first metal oxide is formed, the first metal oxide is crystallized, and the same composition is formed on the first metal oxide. The second metal oxide film is formed, and the thickness of the laminated metal oxide film including the first metal oxide and the second metal oxide film is set to 4 n in any region of the lower electrode.
It is formed within a range of m to 7 nm or within a film thickness distribution of 20% or less.

Such a laminated metal oxide film having a film thickness in the range of 4 nm to 7 nm or a film thickness distribution of 20% or less is formed by using a CVD apparatus provided with a hot wall to measure the temperature of the wall (wall). Can be formed under the same or higher conditions as the substrate temperature. At this time, oxygen (O ₂ ) is used as a source gas for supplying oxygen.

Further, such a laminated metal oxide film has a CV
Using a D apparatus, the substrate temperature is formed under conditions higher than the wall temperature of the CVD apparatus. In order to increase the reaction temperature and promote the surface diffusion of the reaction product, dinitrogen oxide (N) is used as a source gas for supplying oxygen. _It can be formed by using 2O).

Tantalum oxide can be exemplified as the laminated metal oxide film. Further, the present manufacturing method can be applied to a lower electrode (first electrode) formed by roughening a silicon film and vapor-phase doping impurities into the silicon film. In this case, the surface of the silicon film is thermally nitrided. Can be. Further, a metal film or a metal compound can be applied to the lower electrode, and when the lower electrode is made of a metal film or a metal compound,
The silicon nitride film may be formed by using the VD method.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

A method of manufacturing a DRAM according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS. The left part of each drawing showing the cross section of the substrate shows a region (memory cell array) in which a memory cell of the DRAM is formed.
The right part shows the peripheral circuit area.

As shown in FIG. 1, a memory cell selection MISF is formed on a main surface of a semiconductor substrate (hereinafter, simply referred to as a substrate) 1.
ETQs, n-channel MISFETs Qn of peripheral circuits,
A p-channel type MISFET Qp is formed. These MI
The SFET is formed as follows.

An element isolation groove 2 is formed in a substrate 1 and, for example, a silicon oxide film is buried in the element isolation groove 2 and then polished by a CMP (Chemical Mechanical Polishing) method to form an element isolation region 7. Then, a p-type impurity (boron) and an n-type impurity (for example, phosphorus)
Are implanted, and the impurities are diffused by a heat treatment at about 1000 ° C. to form a p-type well 3 and an n-type well 5 on the substrate 1 of the memory cell array, and the p-type well 3 is formed on the substrate 1 of the peripheral circuit region. And n-type well 4
To form Next, a clean gate oxide film 8 is formed in each of the p-type well 3 and the n-type well 4 by using, for example, a thermal oxidation method, and for example, a low-resistance polycrystalline silicon film doped with phosphorus (P) and a WN film. , W film, and further, a silicon oxide film and a silicon nitride film are sequentially deposited. After the silicon nitride film is etched into a predetermined pattern, the silicon oxide film, the W film, the WN film, and the polycrystalline silicon film are etched using the patterned silicon nitride film as a mask. Thereby, a gate electrode 9 made of a polycrystalline silicon film, a WN film and a W film is formed in the memory cell array and the peripheral circuit region, and a cap insulating film 10 made of a silicon oxide film and a silicon nitride film is formed on the gate electrode 9. Form. Note that the gate electrode 9 formed in the memory cell array functions as a word line WL.

Next, the p-type wells 3 on both sides of the gate electrode 9 are formed.
-Type semiconductor region 12 ^- p by -type semiconductor region 11, ion implantation of p-type impurity (boron) in the n-type well 4 ^- n by ion implantation of n-type impurity (phosphorus or arsenic) to I do. Thereafter, a silicon nitride film 13 is deposited on the substrate 1 by, for example, a CVD method, and then the upper part of the substrate 1 of the memory cell array is covered with a photoresist film (not shown), and the silicon nitride film 13 in the peripheral circuit region is anisotropically. To form a sidewall spacer 13a on the side wall of the gate electrode 9 in the peripheral circuit region. Further, an n ⁺ -type semiconductor region 14 (source, drain) is formed by ion-implanting an n-type impurity (phosphor or arsenic) into the p-type well 3 in the peripheral circuit region, and the p-type impurity (boron) is formed in the n-type well 4. )
Implanted into the p ⁺ type semiconductor region 1
5 (source, drain) is formed. In the steps up to this point, the n-channel MISFET with the source and drain of LDD (Lightly Doped Drain) structure in the peripheral circuit area
Qn and p-channel type MISFETs Qp are formed.

Next, as shown in FIG. 2, an interlayer insulating film (silicon oxide film 16) covering the gate electrode 9 and the cap insulating film 10 is formed, and the plugs 20 and 27, the bit line BL, and the first layer are formed. The wirings 30 to 33 are formed. These are formed as follows.

A silicon oxide film 16 flattened by the CMP method is formed on the gate electrode 9, and the silicon oxide film 16 of the memory cell array is dry-etched using a photoresist film (not shown) as a mask. Thereafter, the silicon nitride film 13 under the silicon oxide film 16 is dry etched to form contact holes 18 and 19 above the n ⁻ type semiconductor region 11. The etching of the silicon oxide film 16 is performed under conditions such that the etching rate of silicon oxide is higher than that of silicon nitride, so that the silicon nitride film 13 is not completely removed. The etching of the silicon nitride film 13 is performed under such conditions that the etching rate of silicon nitride is higher than that of silicon (substrate) or silicon oxide.
The substrate 1 and the element isolation region 7 are prevented from being shaved deeply. Further, the etching of the silicon nitride film 13 is performed under such a condition that the silicon nitride film 13 is anisotropically etched, so that the silicon nitride film 13 is left on the side wall of the gate electrode 9 (word line WL). Thus, contact holes 18 and 19 having a fine diameter are formed in a self-alignment (self-alignment) with the gate electrode 9 (word line WL).

Subsequently, an n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 3 (n ^- type semiconductor region 11) of the memory cell array through the contact holes 18 and 19. Thereby, the n ⁺ type semiconductor region 17 (source,
Drain). In the steps up to this point, the memory cell selection M
ISFET Qs is formed.

Thereafter, a low-resistance polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) is deposited inside the contact holes 18 and 19 by a CVD method, and then the polycrystalline silicon film is etched back. The plug 20 is formed by polishing (or polishing by a CMP method). Further, after depositing a silicon oxide film 21 on the silicon oxide film 16 by, for example, the CVD method, the silicon oxide film 21 in the peripheral circuit region and the silicon under the silicon oxide film 21 by dry etching using a photoresist film (not shown) as a mask. By dry-etching the oxide film 16, a contact hole 22 is formed above the source and drain (n ⁺ type semiconductor region 14) of the n-channel type MISFET Qn.
The source and drain (p) of the p-channel type MISFET Qp
^A contact hole 23 is formed above the ⁺ type semiconductor region 15). At this time, simultaneously, a contact hole 24 is formed above the gate electrode 9 of the p-channel MISFET Qp in the peripheral circuit region (and the gate electrode 9 in a region (not shown) of the n-channel MISFET Qn). A through hole 25 is formed in the upper part.

Next, the surface of the source and drain (n ⁺ type semiconductor region 14) of the n-channel MISFET Qn, the surface of the source and drain (p ⁺ type semiconductor region 15) of the p-channel MISFET Qp, and the inside of the contact hole 18 After forming the silicide films 26 on the surfaces of the plugs 20, respectively, the plugs 27 are formed inside the contact holes 22, 23, 24 and inside the through holes 25. The silicide film 26 is formed, for example, in the contact hole 2
The substrate 1 is formed by depositing a Ti film and a TiN film on the silicon oxide film 21 including the insides of 2, 23 and 24 and the inside of the through hole 25 by, for example, a sputtering method, and then subjecting the substrate 1 to a heat treatment. The plug 27 is formed, for example, by depositing a TiN film and a W film on the TiN film by the CVD method, and then polishing the W film, the TiN film and the Ti film on the silicon oxide film 21 by the CMP method, and polishing these films. It is formed by leaving only inside the contact holes 22, 23, and 24 and inside the through hole 25.

Next, a bit line BL is formed above the silicon oxide film 21 in the memory cell array, and first-layer wirings 30 to 33 are formed above the silicon oxide film 21 in the peripheral circuit region. Bit line BL and first layer wirings 30 to 3
3 is formed by, for example, depositing a W film on the silicon oxide film 21 by, for example, a sputtering method, and then dry-etching the W film using a photoresist film as a mask. At this time, the bit line BL and the wiring 30
Since the silicon oxide film 16 under the layers 33 to 33 is flattened, the bit lines BL and the wirings 30 to 33 can be patterned with high dimensional accuracy.

Next, as shown in FIG. 3, a silicon oxide film 34 is formed on the bit line BL and the first layer wirings 30 to 33 in the same manner as the silicon oxide film 16. Then, a through hole 38 is formed. The through hole 38 can be formed with a small opening diameter by using a polycrystalline silicon film as a hard mask and forming a sidewall in a hole opened in the polycrystalline silicon film. After that, a plug 39 is formed inside the through hole 38. The plug 39 can be formed, for example, by depositing a low-resistance polycrystalline silicon film doped with an n-type impurity (phosphorus) using a CVD method and etching back to leave the polycrystalline silicon film only inside the through hole 38. . Further, for example, CV
A silicon nitride film 40 is deposited by the D method, and then the silicon oxide film 4 is formed on the silicon nitride film 40 by, for example, the CVD method.
1 is deposited. Then, a photoresist film (not shown)
Is used as a mask to dry-etch the silicon oxide film 41 of the memory array, and then dry-etch the silicon nitride film 40 under the silicon oxide film 41 to form a deep hole 42 above the through hole 38.
Since the lower electrode of the information storage capacitance element is formed along the inner wall of the deep hole 42, a silicon oxide film forming the deep hole 42 is required to increase the surface area of the lower electrode and increase the amount of accumulated charge. 41 is a thick film (for example, about 1.3 μm)
Is deposited. The opening diameter of the deep hole 42 is 0.3 μm.
And formed with dimensions corresponding to a highly integrated DRAM. As described above, the aspect ratio of the deep hole 42 of the present embodiment is 3 or more, and in the formation of the capacitor insulating film by a normal method, there is a distribution in the film thickness at the bottom portion and the upper portion of the deep hole 42. However, in the present embodiment, as described later, the capacitor insulating film is formed uniformly (uniformly).

Next, as shown in FIG. 4, an amorphous silicon film 43a doped with an n-type impurity (phosphorus) is formed on the silicon oxide film 41 including the inside of the deep hole 42 by CV.
After the deposition by the method D, the amorphous silicon film 43a on the silicon oxide film 41 is etched back to form the amorphous silicon film 4 along the inner wall of the deep hole 42.
Leave 3a. The thickness of the amorphous silicon film 43a is 5
It is about 0 nm.

In place of the above-described method, after the amorphous silicon film 43a is deposited by the CVD method,
For example, a silicon oxide film or an SOG film is formed to bury the amorphous silicon film 43a in a region other than the deep hole 42 together with the silicon oxide film or the SOG film by, for example, a CMP method or an etch-back method. Silicon oxide film or SOG
The film may be removed to leave the amorphous silicon film 43a along the inner wall of the deep hole 42.

Next, as shown in FIG. 5, after the surface of the amorphous silicon film 43a remaining inside the deep hole 42 is wet-cleaned with a hydrofluoric acid-based cleaning solution, the surface of the amorphous silicon film 43a is reduced in a reduced pressure atmosphere. Monosilane (S
iH ₄ ) is supplied, and then the substrate 1 is heat-treated to polycrystallize the amorphous silicon film 43a and grow silicon grains on the surface thereof. Thus, a polycrystalline silicon film 43 having a roughened surface is formed along the inner wall of deep hole 42. This polycrystalline silicon film 43 is used as a lower electrode of an information storage capacitor.

There are various methods for forming irregularities (roughening) on the lower electrode to increase the capacitance. In the present embodiment, the above-described method of growing crystal grains from amorphous silicon is employed because of good controllability of the density and size of the irregularities (silicon grains). According to this method, silicon atoms move by heat treatment in a transition temperature region where amorphous silicon is polycrystallized to form hemispherical crystal grains,
This is a means for forming irregularities on the surface by this hemispherical shape.
This is a phenomenon peculiar to amorphous silicon, and is characterized in that the formation of the irregularities is completed in a self-aligned manner at the time of crystallization. As described above, since silicon grains are grown during the crystallization process from the amorphous silicon film, no silicon grains are formed from the polycrystalline silicon film, and the starting material is in principle amorphous (amorphous silicon film). 43a).

The amount of impurities contained in the starting material (amorphous silicon film 43a) affects the growth of silicon grains. That is, since impurities are a factor that promotes polycrystallization, when many impurities are contained, crystallization ends before silicon grains of a sufficient size are formed, and silicon grains of a required size are formed. I can't grow. For this reason, it is preferable that the impurity contained in the amorphous silicon film 43a as the starting material be 2 × 10 ²⁰ atoms / cm ⁻³ or less. Thus, by suppressing the impurity concentration in the amorphous silicon film 43a to a small value, silicon grains can be grown to a sufficient size.

As described above, as a result of suppressing the amount of impurities contained in the amorphous silicon film 43a, the amount of impurities in the polycrystalline silicon film 43 is reduced, and the capacitor insulating film of the polycrystalline silicon film 43 as the lower electrode is formed. There is a possibility that a depletion problem in which a depletion region is formed at the interface with the semiconductor may occur. In order to suppress this, after the crystallization (after the formation of the polycrystalline silicon film 43), for example, vapor-phase doping that heat-treats the polycrystalline silicon film 43 in a gas atmosphere containing impurities such as phosphine can be applied. As a result, the surface of the polycrystalline silicon film 43 can be doped with impurities at a high density. By performing such gas phase doping, the amount of impurities in the polycrystalline silicon film 43 can be increased, and the problem of depletion can be avoided.

Next, as shown in FIG. 6, a capacitor insulating film 44 is formed on the silicon oxide film 41 including the inside of the deep hole 42. The formation of the capacitor insulating film 44 is performed as follows. This will be described in detail with reference to FIG. FIG.
FIG. 7D is an enlarged sectional view of a portion A in FIG. 6.
In FIGS. 7A to 7D, the shape of the granular silicon is omitted.

First, as shown in FIG. 7A, a silicon nitride film 44a is formed on a polycrystalline silicon film 43. The silicon nitride film 44a is made of, for example, ammonia (NH ₃ ).
It is formed by thermal nitridation by heat treatment in an atmosphere. The thickness of the silicon nitride film 44a is, for example, 1.5 nm.

The formation of the silicon nitride film 44a is performed continuously from the step of doping impurities in the polycrystalline silicon film 43 in the vapor phase without passing through the atmosphere. As a result, vapor-phase doping of impurities can be performed effectively. That is, if the substrate is exposed to the atmosphere after the gas phase doping, a natural oxide film (silicon oxide film) is formed on the surface of the polycrystalline silicon film 43. Such a natural oxide film is not preferable because it increases the effective film thickness of the capacitor insulating film 44, and needs to be etched with hydrofluoric acid or the like. However, if etching with hydrofluoric acid or the like is performed at this stage, the surface portion of the vapor-doped polycrystalline silicon film 43 is also etched at the same time, and the doped impurities are also etched and removed at the same time. The effect is diminished. However, according to the present embodiment in which the silicon nitride film 44a is formed continuously without breaking in vacuum, that is, without releasing to the atmosphere, the effect of the gas-phase doping is not reduced. The silicon nitride film 4
4a may be formed by film deposition by the CVD method.

Next, a first tantalum oxide film 44b having a thickness of, for example, 3 nm is deposited on the silicon nitride film 44a.
The tantalum oxide film 44b is deposited, for example, by a CVD method using pentaethoxy tantalum and oxygen as source gases. By using the CVD method, the first tantalum oxide film 44b can be deposited with good step coverage, but it is difficult to deposit uniformly in the deep hole 42 having an aspect ratio of 3 or more as in this embodiment. Therefore, in this embodiment mode, a hot-wall type CVD apparatus in which the reaction pressure is reduced to about 50 Pa and the wall surface of the reaction vessel is heated is used. Further, the first tantalum oxide film 44b is deposited by lowering the substrate temperature to about 440 ° C.

By lowering the reaction pressure in this manner, the mean free path of the gas in the reaction chamber is lengthened, and the gas supply is promoted so that the gas reaches the bottom of the deep hole 42.
If the raw material gas is also supplied to the bottom of the deep hole 42, there is an effect of making the film thickness of the bottom of the deep hole 42 and the film thickness of the upper portion uniform.

By lowering the substrate temperature to about 440 ° C. using a hot-wall type CVD apparatus, the surface diffusion of the reactive gas molecules on the substrate surface can be promoted.
The promotion of surface diffusion has the effect of improving the uniformity of the first tantalum oxide film 44b and making the film thickness distribution uniform. By these effects, the thickness of the bottom portion of the deep hole 42 of the first tantalum oxide film 44b and the thickness of the top portion thereof can be made uniform. In addition,
At this stage, the first tantalum oxide film 44b is amorphous because it is deposited at a low temperature.

It is preferable that the wall surface temperature of the hot wall type CVD apparatus be higher than the substrate temperature. The wall surface temperature is a gas temperature in a thermal equilibrium state, which means that the temperature of the reaction gas is higher than the substrate temperature. The reaction gas having a temperature higher than the substrate temperature can easily desorb from the substrate surface even when it reaches the substrate surface, and is repeatedly adsorbed and desorbed on the surface, and is observed phenomenologically to migrate to the surface. Such a phenomenon is the promotion of surface diffusion, which contributes to the improvement of the uniformity of the coating. According to the study of the present inventors, such a phenomenon is observed when oxygen is used as the oxidizing agent.

Next, as shown in FIG. 7B, the first tantalum oxide film 44b is subjected to a heat treatment, and the first tantalum oxide film 44b is crystallized to form a polycrystalline tantalum oxide film 44c. The heat treatment is performed, for example, at 800 ° C. in an oxygen atmosphere.
A condition for 3 minutes can be exemplified. By performing the heat treatment in an oxygen atmosphere, the first tantalum oxide film 44b is crystallized, and oxygen defects in the polycrystalline tantalum oxide film 44c can be recovered to reduce the leak current of the polycrystalline tantalum oxide film 44c.

At the time of this heat treatment, the silicon nitride film 44a
Functions as a diffusion preventing film or an oxidation preventing film for preventing diffusion of oxygen atoms permeating the polycrystalline tantalum oxide film 44c to the surface of the polycrystalline silicon film 43. This prevents formation of a silicon oxide film having a low dielectric constant on the surface of the polycrystalline silicon film 43 and prevents an increase in the effective film thickness of the capacitor insulating film 44. During this heat treatment, the silicon nitride film 4
4a is converted to a silicon oxynitride film 44d. The thickness of the silicon oxynitride film 44d is 3.0 nm, which is larger than 1.5 nm of the silicon nitride film 44a.

In the present heat treatment step, the heat treatment in an oxygen atmosphere has been described as an example. However, the heat treatment is not limited to oxygen, and may be an oxidizing atmosphere. In addition, the example in which the crystallization and the oxidation are performed simultaneously has been described. However, these processes may be performed separately. That is, after crystallization by heat treatment in a non-oxidizing atmosphere such as nitrogen, recovery of oxygen defects may be achieved by treatment in an oxidizing atmosphere. After the crystallization treatment, the oxidation treatment may not be performed, and the oxidation treatment may be collectively performed after the formation of the second tantalum oxide film described below.

Next, as shown in FIG. 7C, a second tantalum oxide film 44e is formed under the same conditions as those for the first tantalum oxide film 44b. That is, the second tantalum oxide film 44e is formed using a hot wall type CVD apparatus at a low pressure and at a low substrate temperature. The thickness of the second tantalum oxide film 44e is, for example, 4 nm. The total thickness of the first tantalum oxide film 44b and the second tantalum oxide film 44e is set to 7 nm. Here, the film thickness refers to the film thickness above the deep hole 42 or the upper surface of the silicon oxide film 41. The above-mentioned first tantalum oxide film 4
Similarly to 4b, since the second tantalum oxide film 44e is formed using the hot wall type CVD apparatus, the second tantalum oxide film 44e is formed even at the bottom or the top of the deep hole 42.

The second tantalum oxide film 44e is formed in a state where it has already been crystallized, although the crystallization heat treatment is not performed at this stage. That is, since the polycrystalline tantalum oxide film 44c, which is the base of the second tantalum oxide film 44e, is in a polycrystalline state, it becomes a crystal nucleus and a kind of epitaxial growth occurs. Therefore, the second tantalum oxide film 44e is formed as a polycrystalline thin film, despite being formed at a low temperature (about 440 ° C.).

Since the second tantalum oxide film 44e is formed in a polycrystalline state, even if the capacitor insulating film is formed in an as-deposited state, a leak current at a level that does not cause any practical problem can be realized. However, oxygen vacancies exist in the second tantalum oxide film 44e, and it is preferable to perform an oxidizing heat treatment for recovering the oxygen vacancies in order to more reliably suppress the leak current. The conditions of this heat treatment are as follows:
A condition at 0 ° C. for 2 minutes can be exemplified. It is the same as described above that an oxidizing atmosphere may be used instead of the oxygen atmosphere.

Thus, the capacitor insulating film 44 composed of the polycrystalline tantalum oxide film having the two-layer structure of the upper layer (second tantalum oxide film 44e) and the lower layer (polycrystalline tantalum oxide film 44c) and the silicon oxynitride film 44d Is formed.

Since the polycrystalline tantalum oxide film thus formed is formed by the hot wall CVD apparatus under the above-mentioned conditions, the film thickness at the top or bottom of the deep hole 42 is formed uniformly. The thickness is formed in the range of 7 nm to 4 nm. That is, the deep hole 4 having the largest film thickness
The upper portion 2 has a thickness of 7 nm or less, and the bottom portion of the deep hole 42 has a thickness of 4 nm or more. The thickness of the two-layered polycrystalline tantalum oxide film formed in this manner has a thickness distribution of 20 in any region of the deep hole 42.
% Is formed. By uniformly forming the polycrystalline tantalum oxide film in this manner, the capacitance value of the DRAM can be increased and the reliability can be increased.

Further, by forming the polycrystalline tantalum oxide film into a two-layer structure, the leakage current can be reduced. That is,
The grain boundary that serves as a path for the leakage current may be an upper layer (second tantalum oxide film 44e) or a lower layer (polycrystalline tantalum oxide film 44e).
Since they are separated from each other in c), the grain boundaries do not penetrate the polycrystalline tantalum oxide film. For this reason, the leakage current caused by the grain boundary can be suppressed to a small value.

The lower layer (polycrystalline tantalum oxide film 44)
The thickness of c) is smaller than the thickness of the upper layer (second tantalum oxide film 44e). By thus making the lower layer thin, the total heat load can be reduced. That is, since the lower first tantalum oxide film 44b is amorphous in the as-deposited state, a heat treatment for crystallizing it is necessary. However, the upper second tantalum oxide film 44e is polycrystalline in the as-deposited state. is there. Therefore, the second tantalum oxide film 44e
No heat treatment for crystallizing is required. The heat treatment load can be reduced by this amount. Then, the first tantalum oxide film 4
The load of the crystallization heat treatment of 4b is the first tantalum oxide film 44b.
Can be reduced as the film thickness is smaller. Therefore, when the lower layer is configured to be thin as in the present embodiment, the total heat treatment load can be reduced. Even if the lower layer is thin, it is sufficient that the lower layer is crystallized when forming the upper layer, and the total polycrystalline tantalum oxide film thickness is
You can earn 4e. Note that the lower first tantalum oxide film 44b (polycrystalline tantalum oxide film 44c) does not need to be a complete film. Even if the first tantalum oxide film 44b (polycrystalline tantalum oxide film 44c) is formed not in a film but in an island shape, the total polycrystalline tantalum oxide film thickness can be maintained by the upper second tantalum oxide film 44e, Even if the first tantalum oxide film 44b (polycrystalline tantalum oxide film 44c) is formed in an island shape, the island-shaped polycrystalline tantalum oxide film 44c becomes a crystal nucleus during the deposition of the second tantalum oxide film 44e. This is because the second tantalum oxide film 44e is formed by crystallization in an as-deposited state.

FIG. 8 shows the lower electrode (polycrystalline silicon film 43) and capacitor insulating film 4 formed by the method described above.
FIG. 4 is a schematic cross-sectional view of the result of observing No. 4 with a transmission electron microscope (TEM). As shown in FIG. 8, granular silicon (unevenness)
Over the entire region including the surface of the polysilicon film 4
It can be seen that a silicon oxynitride film 44d, a polycrystalline tantalum oxide film 44c (lower layer), and a second tantalum oxide film 44e (upper layer) are formed on 3 (lower electrode) with a uniform (uniform) film thickness. In such a cross-sectional TEM observation, the thickness of the polycrystalline tantalum oxide film 44c (lower layer) and the thickness of the second tantalum oxide film 44e (upper layer) are 5.5 nm in the region located at the bottom of the deep hole 42. It was 6.5 nm in the region located above 42. Further, in the entire region of the deep hole 42, the film thickness was within the range of 7 to 4 nm.

Next, as shown in FIG. 7D, a TiN film 45 is deposited on the second tantalum oxide film 44e (capacitor insulating film 44) by using, for example, a CVD method and a sputtering method. Thereafter, using a photoresist film (not shown) as a mask, the TiN film 45 and the capacitor insulating film 4 are formed.
4 is dry-etched to form a TiN film 45.
An information storage capacitance element C composed of an upper electrode made of, a capacitor insulating film 44 and a lower electrode made of a polycrystalline silicon film 43 is formed (FIG. 9). Through the steps so far, a DRAM memory cell including the memory cell selecting MISFET Qs and the information storage capacitor C connected in series thereto is completed.

Next, as shown in FIG. 10, a second layer Al wiring is formed on the information storage capacitor C by the following method.

First, a silicon oxide film 50 is deposited on the information storage capacitive element C by, for example, the CVD method, and the first layer wirings 30 and 33 in the peripheral circuit region are formed using a photoresist film (not shown) as a mask. Upper silicon oxide film 50, 4
1. Through-holes 51, 5 are formed by dry-etching silicon nitride film 40 and silicon oxide film 34.
Form 2 After that, a plug 53 is formed inside the through holes 51 and 52. The plug 53 is formed, for example, by depositing a TiN film on the silicon oxide film 50 by a sputtering method and further depositing a W film on the TiN film by a CVD method.
These films are etched back to form through holes 51 and 52.
It is formed by leaving inside.

Next, second layer wirings 54 to 56 are formed on the silicon oxide film 50. The wirings 54 to 56 are formed on the silicon oxide film 50 by sputtering, for example.
After depositing an iN film, an Al (aluminum) alloy film and a Ti film, these films are formed by dry etching using a photoresist film (not shown) as a mask.

Thereafter, a third-layer wiring, a further upper-layer wiring, a passivation film, and the like can be formed in the same manner, but illustration thereof is omitted. Through the above steps, the DRAM of the present embodiment is substantially completed.

FIGS. 11 and 12 are graphs for evaluating the characteristics of the capacitor (information storage capacitance element C) formed in the present embodiment. In the evaluation of characteristics, in a group of capacitors in which 8000 bits of capacitors were connected in parallel, the lower electrode was grounded, a voltage was applied to the upper electrode, and a leak current flowing between the upper and lower electrodes was detected. In each graph, the leak current is converted into a current value per bit.

FIG. 11 shows typical leakage current characteristics. The horizontal axis shows the voltage applied to the upper electrode, and the vertical axis shows the leak current value per bit. An important characteristic parameter in a DRAM is information retention time. In order to lengthen the information holding time, it is preferable that the leak current is as small as possible. However, since the leak current cannot be actually reduced to zero, for example, a criterion for determining whether or not the leak current value when 1 V is applied exceeds 1 fA can be adopted as an index for judging the quality. Referring to FIG.
The RAM does not exceed 1 fA, and it can be determined that the characteristics are good.

FIG. 12 is a graph showing the dependence of the leakage current and the capacitance value of the capacitor on the thickness of the tantalum oxide film. The capacitance value of the capacitor is represented by an effective film thickness converted into a silicon oxide film. The left vertical axis shows the leak current value when 1 V is applied (current value corresponding to point A in FIG. 11).
The right vertical axis indicates the effective film thickness obtained from the capacitance obtained per bit. The smaller the effective film thickness, the larger the capacity.

As shown in FIG. 12, the leak current sharply increases as the thickness of the tantalum oxide film (polycrystalline tantalum oxide film 44c and second tantalum oxide film 44e) decreases. It becomes difficult to secure a leak current value of 1 fA or less when the film thickness is less than 4 nm. This is thought to be because the continuity of the film starts to be lost around the time when the film thickness is less than 4 nm, and when the film thickness is further reduced, the tantalum oxide film is formed only in an island shape (island shape), and as a result, a leakage current is reduced. Seems to increase.

On the other hand, the effective film thickness shows a tendency opposite to that of the leak current, and rapidly increases when the film thickness exceeds about 7 nm. That is, the capacitance value decreases. This is a natural conclusion of physics in which the capacitance value is proportional to the dielectric constant of the insulating film and the area of the capacitor electrode, and is inversely proportional to the thickness of the insulating film (electrode spacing).

In other words, when a tantalum oxide film is used as a capacitor insulating film as in the present embodiment, it is necessary to reduce the leakage current and to secure a larger capacitance value. It is effective to control the thickness of the second tantalum oxide film 44e) to 4 nm to 7 nm, and in the DRAM of the present embodiment,
This has been achieved.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

That is, in the above embodiment, the polycrystalline silicon film 43 is exemplified as the lower electrode, but a metal film or a metal compound film may be used.

For example, as shown in FIG.
A ruthenium (Ru) film 60 may be formed along the inner surface of the substrate to form a lower electrode. In this case, it is preferable to form a barrier metal 61 between the plug 39 and the ruthenium film 60. When the ruthenium film 60 is used for the lower electrode, the silicon nitride film 44a may not be provided as shown in FIG. That is, the first tantalum oxide film 44b is directly deposited on the ruthenium film 60 (FIG. 14A),
The first tantalum oxide film 44b is crystallized to form a polycrystalline tantalum oxide film 44c (FIG. 14B), and a second tantalum oxide film 44e is formed (FIG. 14C). After that, a TiN film 45 is formed (FIG. 14D). In this case, the ruthenium film 60 is oxidized during the crystallization and oxidation reforming of the first tantalum oxide film 44b, but the ruthenium oxide (Ru) which is an oxide of ruthenium is used.
O) is conductive, and the effective film thickness of the capacitor insulating film 44 does not increase even if ruthenium oxide is formed.
Therefore, a silicon nitride film for preventing oxidation of the lower electrode surface is not required. In this oxidation process, the barrier metal 61 functions as an oxidation prevention film for the plug 39.

As shown in FIG. 15, a titanium nitride film 62 may be formed along the inner surface of the deep hole 42 to form a lower electrode. When the titanium nitride film 62 is used for the lower electrode, it is preferable to provide a silicon nitride film 44a as shown in FIG. That is, a silicon nitride film 44a is formed on the titanium nitride film 62, and a first tantalum oxide film 44b is deposited on the silicon nitride film 44a (FIG. 16).
(A)), the first tantalum oxide film 44b is crystallized into a polycrystalline tantalum oxide film 44c, and the silicon nitride film 44a is converted into a silicon oxynitride film 44d (FIG. 16).
(B)). Thereafter, a second tantalum oxide film 44e is formed (FIG. 16C). Further, a TiN film 45 is formed (FIG. 16D). If the titanium nitride film 62 is oxidized during the crystallization and oxidation reforming of the first tantalum oxide film 44b, titanium oxide having a low dielectric constant is formed, which is not preferable. However, here, the silicon nitride film 44a is formed, and the titanium nitride film 62 is not oxidized.

In the above embodiment, the case where the capacitor insulating film 44 includes a tantalum oxide film has been described. However, the invention is not limited to the tantalum oxide film, and a metal oxide film having a high dielectric constant can be applied. For example, PZT, PLT, PLZ
T, PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , BS
It is a high dielectric or ferroelectric substance having a perovskite-type or composite perovskite-type crystal structure such as T or SBT. When these metal oxide films are deposited by the CVD method, an organic source is used similarly to tantalum oxide. When the manufacturing method of the present embodiment is applied, the film thickness distribution can be similarly made uniform.

Further, in the above-described embodiment, an example has been described in which, when the tantalum oxide film is deposited by the CVD method, oxygen is used as an oxidizing agent, the substrate temperature is lowered, and a hot wall type device is used. As an example, dinitrogen oxide (N ₂ O) may be used, and the tantalum oxide film may be deposited under the condition that the substrate temperature is higher than the wall surface temperature of the CVD apparatus. in this case,
Unlike the case where oxygen is used as the oxidizing agent, by using N ₂ O as the oxidizing agent, the reaction temperature with pentaethoxy tantalum can be increased to about 600 ° C., and as a result, the substrate temperature can be increased. A film can be formed, and a precursor of film formation such as a cluster and an active molecule attached to the substrate can be separated or subjected to surface migration by thermal energy of the substrate. Such a situation has the effect of promoting surface diffusion, and can improve the uniformity of the film thickness. Thereby, the same effect as in the embodiment can be obtained.

In the above embodiment, the case where the present invention is applied to a DRAM has been described. However, the present invention is not limited to this, and is widely applied as a method of forming an insulating film of an LSI manufactured with a design rule of 0.25 μm or less. can do.

[0079]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) A highly uniform capacitor insulating film can be formed even in a deep hole having an aspect ratio as high as 3 or more.

(2) Even when the lower electrode having the irregularities formed on the surface is formed in the deep hole, a highly uniform capacitor insulating film can be formed.

(3) The DRA which is easy to secure the capacitance value of the capacitor, has high reliability, and is advantageous for low power consumption
M can be configured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 3 is a cross-sectional view showing a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 4 is a cross-sectional view showing a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 5 is a cross-sectional view showing a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 6 is a cross-sectional view showing a method for manufacturing the DRAM of the embodiment in the order of steps;

FIGS. 7A to 7D are partial cross-sectional views showing an enlarged part A of FIG. 6;

FIG. 8 is a schematic cross-sectional view of a result obtained by observing a lower electrode and a capacitor insulating film of the present embodiment with a transmission electron microscope.

FIG. 9 is a cross-sectional view showing a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 10 is a cross-sectional view showing a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 11 is a graph showing an evaluation of characteristics of a capacitor (information storage capacitor C) formed in the embodiment.

FIG. 12 is a graph showing an evaluation of characteristics of a capacitor (information storage capacitor C) formed in the embodiment.

FIG. 13 is a partial cross-sectional view showing another example of the DRAM of the embodiment;

14A to 14D are partial cross-sectional views illustrating a method of manufacturing another example of the DRAM of the embodiment;

FIG. 15 is a partial cross-sectional view showing still another example of the DRAM of the embodiment;

16A to 16D are partial cross-sectional views illustrating a method of manufacturing still another example of the DRAM according to the embodiment;

[Description of Signs] 1 Substrate 2 Element isolation groove 3 P-type well 4 n-type well 5 n-type well 7 element isolation region 8 gate oxide film 9 gate electrode 10 cap insulating film 11 n ^- type semiconductor region 12 p ^- type semiconductor region Reference Signs List 13 silicon nitride film 13a sidewall spacer 14, 17 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 16 silicon oxide film 18, 22-24 contact hole 20, 27, 53 plug 21 silicon oxide film 25, 38, 51 through hole 26 silicide film 30-33 First layer wiring 34 silicon oxide film 39 plug 40 silicon nitride film 41 silicon oxide film 42 deep hole 43 polycrystalline silicon film 43a amorphous silicon film 44 capacitor insulating film 44a silicon nitride film 44b first tantalum oxide Film 44c polycrystalline tantalum oxide film 4d Silicon oxynitride film 44e Second tantalum oxide film 45 TiN film 50 Silicon oxide film 54 to 56 Second layer wiring 60 Ruthenium film 61 Barrier metal 62 Titanium nitride film BL Bit line C Information storage capacitor Qnn n-channel MISFET Qp P-channel type MISFET Qs MISFET for memory cell selection WL Word line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Ryoichi Furukawa, 6-16-16, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. 3 F term in Hitachi, Ltd. Device Development Center (reference) 5F083 AD10 AD31 AD48 AD49 AD60 AD62 GA06 GA25 JA05 JA06 JA13 JA14 JA15 JA35 JA38 JA39 JA40 JA43 KA20 MA03 MA06 MA17 MA19 MA20 PR12 PR15 PR21 PR23 PR33 PR39 PR40 PR42 PR43 PR44 PR45 PR52 PR53 PR54 PR55

Claims (9)

[Claims] A first electrode having a three-dimensional structure;
A semiconductor device including an information storage capacitive element including a second electrode formed to face an electrode and a capacitor insulating film formed between the first and second electrodes, wherein the capacitor insulating film comprises: A metal oxide compound film having a high dielectric constant, wherein the metal oxide compound film has a thickness in a range of 4 nm to 7 nm or a thickness distribution thereof in any region between the first and second electrodes; Is within 20%. 2. The semiconductor device according to claim 1, wherein said metal oxide compound film is a crystallized tantalum oxide film. 3. The semiconductor device according to claim 2, wherein the crystallized tantalum oxide film includes a first tantalum oxide film provided on the first electrode side and a second tantalum oxide film provided on the second electrode side. A semiconductor device, comprising: a tantalum dioxide film, wherein a thickness of the first tantalum oxide film is smaller than a thickness of the second tantalum oxide film. 4. The semiconductor device according to claim 1, wherein the capacitor insulating film includes a silicon oxynitride film formed in contact with the first electrode. Characteristic semiconductor device. 5. The semiconductor device according to claim 1, wherein the first electrode is made of polycrystalline silicon having a roughened surface, or a metal or a metal compound. A semiconductor device characterized by the above-mentioned. 6. A step of forming a first electrode having a three-dimensional structure;
A first method including a step of forming a metal oxide film and a step of crystallizing the metal oxide film, or a step of forming a first electrode having a three-dimensional structure, and a step of forming a film or island. Forming a first metal oxide; crystallizing the first metal oxide;
A second metal oxide having the same composition as the first metal oxide is formed on the metal oxide.
Forming a metal oxide film, wherein the metal oxide film or the first metal oxide and the second metal oxide film
The laminated metal oxide film made of a metal oxide film has a thickness of 4 nm in any region of the first electrode having the three-dimensional structure.
A method of manufacturing a semiconductor device, wherein the semiconductor device is formed within a range of about 7 nm or within a thickness distribution of 20% or less. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the metal oxide film or the first metal oxide film and the second metal oxide film are formed using a CVD device having a hot wall. A first method in which the temperature of the hot wall is higher than a substrate temperature and oxygen (O ₂ ) is used as a source gas for supplying oxygen, or the metal oxide film or the first metal oxide and the first method. The bimetal oxide film is formed on the substrate by using a CVD apparatus and the substrate temperature is set at the CV.
2. A method of manufacturing a semiconductor device, comprising: a second method in which the device is formed at a temperature higher than the wall temperature of the device D, and nitrous oxide (N ₂ O) is used as a source gas for supplying oxygen. Method. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the metal oxide film or the first metal oxide film and the second metal oxide film are made of tantalum oxide. A method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 6, wherein the first electrode is formed by roughening a silicon film and vapor-doping an impurity into the silicon film. After the configuration, a first step of thermally nitriding the surface of the silicon film, a second step of forming a metal film or a metal compound to form the first electrode, forming a metal film or a metal compound, And a third step of forming a silicon nitride film on the first electrode by using a CVD method after forming the first electrode.