KR19980030941A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR19980030941A KR19980030941A KR1019960050422A KR19960050422A KR19980030941A KR 19980030941 A KR19980030941 A KR 19980030941A KR 1019960050422 A KR1019960050422 A KR 1019960050422A KR 19960050422 A KR19960050422 A KR 19960050422A KR 19980030941 A KR19980030941 A KR 19980030941A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- semiconductor device
- nsg
- doped
- interlayer insulating
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 238000011065 in-situ storage Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000003068 static effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000075 oxide glass Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치의 층간절연막 형성 기술.Interlayer insulating film formation technology of semiconductor device.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
반도체 장치의 층간절연막을 형성함에 있어, 공정시간의 단축을 가져와 생산성을 향상시키고자 함.In forming an interlayer insulating film of a semiconductor device, the process time is shortened to improve productivity.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
층간절연막으로 NSG막과 BPSG막을 인-시츄로 연속적으로 형성한다.An NSG film and a BPSG film are successively formed in-situ as an interlayer insulating film.
4. 발명의 중요한 용도4. Important uses of the invention
SRAM 등을 포함하는 반도체 장치Semiconductor device including SRAM
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 스태틱 램(stactic RAM) 제조에서 로드(Load) 폴리실리콘층 상의 층간절연막을 비도핑된 산화막(NSG: Nondoped Silicate Glass)과 BPSG층으로 사용하여 상기 두층을 연속적으로 증착할 수 있는 SRAM 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the manufacture of a static RAM, an interlayer insulating layer on a load polysilicon layer is used as a non-doped oxide glass (NSG) and a BPSG layer. The present invention relates to a SRAM manufacturing method capable of depositing continuously.
도 1을 참조하여 종래의 SRAM 제조 방법을 살펴본다.Referring to Figure 1 looks at a conventional SRAM manufacturing method.
도 1에 도시된 바와같이 종래에는 실리콘 기판(11) 상에 통상의 소정 공정으로 하부층(12)들을 형성하고 SRAM을 구성하는 로드 저항용 폴리실리콘층(13)을 형성한 다음, 층간절연막으로 TEOS(tetraethlyorthosilicate glass)층(14)을 2000Å 정도의 두께로 형성하고 BPSG(borophosphosilicate glass)층(15)을 5000Å 정도 형성한 상태를 나타낸다. 여기서 로드 저항용 폴리실리콘층(13) 상에 바로 BPSG층(15)을 형성하지 않고 TEOS층을 개재하는 이유는 BPSG층에 함유된 불순물이 이후의 공정에서 폴리실리콘막 및 기판으로 확산되어 소자의 특성을 변화시키게 되는 것을 방지하고, 또한 보다 우수한 층간절연을 이루기 위함이다.As shown in FIG. 1, a polysilicon layer 13 for load resistance, which forms a lower layer 12 and forms an SRAM, is formed on a silicon substrate 11 in a conventional predetermined process, and then TEOS is used as an interlayer insulating film. The tetraethlyorthosilicate glass layer 14 is formed to a thickness of about 2000 GPa and the borophosphosilicate glass layer 15 is about 5000 GPa. The reason why the TEOS layer is interposed without forming the BPSG layer 15 directly on the polysilicon layer 13 for the load resistance is that impurities contained in the BPSG layer are diffused into the polysilicon film and the substrate in a subsequent process. This is to prevent the change of characteristics and to achieve better interlayer insulation.
그러나, 종래기술에서 TEOS층(14)은 보통 3∼4 시간 동안 별도의 공정챔버에서 증착이 이루어지기 때문에 공정시간이 상당히 길어지게되며, 또한 TEOS층(14)을 증착한 다음 BPSG층(15)을 증착하는 공정 시간이 12시간 이상 길어지게 되면 H2SO4+ H2O2를 사용하는 별도의 세정공정이 필요시된다. 따라서, 생산성 저하를 가져오는 요인이 된다.However, in the prior art, since the TEOS layer 14 is usually deposited in a separate process chamber for 3 to 4 hours, the processing time becomes considerably longer, and the BPSG layer 15 is deposited after the TEOS layer 14 is deposited. If the process time of depositing longer than 12 hours, a separate cleaning process using H 2 SO 4 + H 2 O 2 is required. Therefore, it becomes a factor which brings about productivity fall.
본 발명은 반도체 장치의 층간절연막을 형성함에 있어 공정시간을 단축하고 생산성을 증가시키는 반도체 장치 제조 방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which shortens the process time and increases productivity in forming an interlayer insulating film of the semiconductor device.
도 1은 종래의 층간절연막 형성 공정도,1 is a process chart for forming a conventional interlayer insulating film,
도 2는 본 발명의 일실시예에 따른 층간절연막 형성 공정도.2 is an interlayer insulating film forming process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21: 실리콘 기판 22: 폴리실리콘층21: silicon substrate 22: polysilicon layer
23: NSG층 24: BPSG층23: NSG layer 24: BPSG layer
상기 목적을 달성하기 위하여 본 발명은 반도체 장치를 구성하는 전도층간의 층간절연막을 비도핑된 산화막(NSG)과 불순물이 도핑된 산화막을 차례로 적층하여 형성하며, 상기 두 층을 상압화학기상증착(APCVD)에서 인-시츄로 연속하여 형성하는 것을 포함한다.In order to achieve the above object, the present invention forms an interlayer insulating film between conductive layers constituting a semiconductor device by sequentially stacking an undoped oxide film (NSG) and an oxide film doped with impurities, wherein the two layers are formed by atmospheric chemical vapor deposition (APCVD). ) To form in-situ in series.
이하, 첨부된 도면 도 2를 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.
도 2에 도시된 바와 같이, 본 발명은 실리콘 기판(21) 상에 통상의 소정 공정으로 하부층(22)과 SRAM의 로드 저항용 폴리실리콘층(23)을 형성한 다음, 400∼450℃에서 SiH4가스 0.024 sccm과 O2가스 0.49 sccm을 사용하여 비도핑된 산화막(24)을 형성하고, 계속해서 인-시츄(In-Situ)로 BPSG층(25)을 증착한 상태이다. 여기서 사용되는 장비는 APCVD(atmospheric pressure CVD)시스템으로 다수의 챔버를 가지고 있어 벨트에 의해 웨이퍼를 이동시키며 인-시츄(In-Situ) 공정을 수행할 수 있는 W-J(WATKINS-JOHNSON) 장비이다. 즉, 본 발명은 W-J 장비를 사용하여 첫 번째 챔버에서 비도핑 산화막을 증착하고 벨트로 웨이퍼를 이동시켜 두 번째 챔버에서 BPSG층이 형성되도록 하는 것이다.As shown in FIG. 2, the present invention forms the lower layer 22 and the polysilicon layer 23 for the load resistance of the SRAM on a silicon substrate 21 in a usual predetermined process, and then SiH at 400 to 450 占 폚. The undoped oxide film 24 was formed using 0.024 sccm of 4 gas and 0.49 sccm of O 2 gas, and the BPSG layer 25 was subsequently deposited in-situ. The equipment used here is an atmospheric pressure CVD (APCVD) system, which is a WJ (WATKINS-JOHNSON) apparatus that has a plurality of chambers, which moves wafers by a belt, and performs an in-situ process. That is, the present invention is to deposit the undoped oxide film in the first chamber using the WJ equipment and to move the wafer to the belt so that the BPSG layer is formed in the second chamber.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.
본 발명은 공정시간을 단축하고 생산성을 증가시키는 효과가 있다.The present invention has the effect of shortening the process time and increasing productivity.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960050422A KR19980030941A (en) | 1996-10-30 | 1996-10-30 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960050422A KR19980030941A (en) | 1996-10-30 | 1996-10-30 | Semiconductor device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980030941A true KR19980030941A (en) | 1998-07-25 |
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ID=66315877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960050422A KR19980030941A (en) | 1996-10-30 | 1996-10-30 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980030941A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990012398A (en) * | 1997-07-29 | 1999-02-25 | 윤종용 | Interlayer insulating film formation method to prevent bit line shift |
| KR100470185B1 (en) * | 1997-12-30 | 2005-05-17 | 주식회사 하이닉스반도체 | Interlayer insulating film formation method of semiconductor device |
-
1996
- 1996-10-30 KR KR1019960050422A patent/KR19980030941A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990012398A (en) * | 1997-07-29 | 1999-02-25 | 윤종용 | Interlayer insulating film formation method to prevent bit line shift |
| KR100470185B1 (en) * | 1997-12-30 | 2005-05-17 | 주식회사 하이닉스반도체 | Interlayer insulating film formation method of semiconductor device |
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