KR950000854B1 - Inter-layer insulating film depositing method - Google Patents

Inter-layer insulating film depositing method Download PDF

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KR950000854B1
KR950000854B1 KR1019910016413A KR910016413A KR950000854B1 KR 950000854 B1 KR950000854 B1 KR 950000854B1 KR 1019910016413 A KR1019910016413 A KR 1019910016413A KR 910016413 A KR910016413 A KR 910016413A KR 950000854 B1 KR950000854 B1 KR 950000854B1
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insulating film
interlayer insulating
film
forming
semiconductor device
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KR1019910016413A
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KR930006835A (en
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김창규
최지현
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

Abstract

The method includes the steps of sequentially forming 1st and 2nd insulating films (25)(27) on the substrate with a conducting pattern (23), forming a SOG (spin on glass) film (29) thereon to etch-back and remove the films (29,27) over the conducting pattern (23), and removing the residual film (29) to grow a 3rd interlayered insulating film (30) at slow growing rate on the film (25) and at rapid growing rate on the film (27), thereby forming a flat interlayered insulating film. The 3rd interlayered insulating film (30) uses an USG (undoped silicate glass) film.

Description

반도체 장치의 층간 절연막 형성방법Method of forming interlayer insulating film of semiconductor device

제 1 도는 종래의 제조 공정도.1 is a conventional manufacturing process diagram.

제 2 도는 본 발명의 따른 제조 공정도.2 is a manufacturing process diagram according to the present invention.

본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 반도체 장치의 층간 절연막 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an interlayer insulating film of a semiconductor device.

최근 반도체 장치의 고집적화 추세에 따라 층간 절연막의 평탄화 공정이 중요한 문제로 대두 되었다.Recently, the planarization of the interlayer insulating film has become an important problem due to the trend of high integration of semiconductor devices.

층간 절연막의 평탄화 공정시 일반적으로 BPSG(Boro-Phospho Silicate Glass)막을 층간 절연막으로 사용하고 있다.In general, a BPSG (Boro-Phospho Silicate Glass) film is used as the interlayer insulating film in the planarization process of the interlayer insulating film.

제 1 (a)∼(c)도는 종래의 제조공정도로서 BPSG막을 층간절연막으로 사용한 경우를 나타낸다. 상기 제 1 (a)도에서 필드산화막(3)이 형성된 제 1 도전형의 반도체 기판(1) 상면에 게이트 산화막(5)을 중간층으로하고 고온산화막(7)으로 둘러싸인 게이트(9)를 형성한다. 상기 제 1 (b)도에서 상기 기판(1) 상면에 층간절연을 위하여 BPSG막(11a)을 형성한다. 그 다음 상기 BPSG막(11)을 리플로우 시켜 상기 기판의 표면을 평탄화한다. 여기서 상기 리플로우 공정시 열에 의해 상기 기판내에 형성된 소정의 접합(junction)이 파괴되기 쉬운 문제점이 있었다. 상기한 문제점을 극복하기 위하여 리플로우 공정의 온도를 낮출 경우에는 평탄도가 저하되는 문제점이 있었다. 또한 BPSG막에 함유된 붕소 및 인의 농도로 인하여 트랜지스터의 특성이 변하게 되는 문제점도 있었다. 따라서 본 발명의 목적은 반도체 장치의 층간 절연막 형성방법에 있어서 우수한 평탄도를 가짐과 동시에 기판내의 접합파괴 없이 리플로우 공정을 실시하기 위한 층간 절연막 형성방법을 제공함에 있다.1 (a) to (c) show a case where a BPSG film is used as an interlayer insulating film as a conventional manufacturing process chart. A gate 9 surrounded by a high temperature oxide film 7 is formed as an intermediate layer on the upper surface of the first conductive semiconductor substrate 1 on which the field oxide film 3 is formed in FIG. . In FIG. 1B, a BPSG film 11a is formed on the upper surface of the substrate 1 for interlayer insulation. Then, the BPSG film 11 is reflowed to planarize the surface of the substrate. Here, there is a problem that a predetermined junction formed in the substrate is easily broken by heat during the reflow process. In order to overcome the above problems, when the temperature of the reflow process is lowered, there is a problem that the flatness is lowered. In addition, there is a problem that the characteristics of the transistor change due to the concentration of boron and phosphorus contained in the BPSG film. Accordingly, an object of the present invention is to provide a method for forming an interlayer insulating film for performing a reflow process with excellent flatness in the method for forming an interlayer insulating film of a semiconductor device and without destroying a junction in a substrate.

본 발명의 다른 목적은 반도체 장치의 층간 절연막 형성방법에 있어서 트랜지스터에 영향을 미치지 않는 층간 절연막 형성방법을 제공함에 있다.Another object of the present invention is to provide a method for forming an interlayer insulating film which does not affect the transistor in the method for forming an interlayer insulating film of a semiconductor device.

상기한 바와 같은 본 발명의 목적을 달성하기 위하여 하지막질에 따라 증착률이 달라지는 하지 의존성을 이용하여 평탄화 공정을 실시하고 반도체 소자에 영향을 미치지 않은 온도범위 내에서 층간 절연막을 경화시킴을 특징으로 한다. 본 발명의 다른 목적을 달성하기 위하여 BPSG막 대신 USG(Undope Silicate Glass)막을 층간 절연막으로 사용함을 특징으로 한다.In order to achieve the object of the present invention as described above, the planarization process is performed by using the dependence of the deposition rate depending on the underlying film quality, and the interlayer insulating film is cured within the temperature range without affecting the semiconductor device. . In order to achieve another object of the present invention, an USG (Undope Silicate Glass) film is used as an interlayer insulating film instead of a BPSG film.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 2 (a)∼(d)도는 본 발명에 따른 층간 절연막의 형성방법을 나타낸 제조 공정도이다. 상기 제 2(a)(b)에서 필드산화막(17), 게이트 산화막(19) 및 고온산화막(21 : HTO(High Temperature Oxide)으로 둘러싸인 게이트(23)가 형성된 제 1 도전형의 반도체 기판(15) 상면에 제 1 층간 절연막(25)과 제 2 층간 절연막(27)을 순차적으로 형성한다. 상기 제 1 층간 절연막(25)은 0.1μm 정도의 두께를 가지는 고온산화막(HTO : High Temperature Oxide), O3-TEOS PSG(O3-Tetraethylorthosilicate Phospho-Silicate-Glass), O3-TEOS BPSG 또는 P-TEOS USG(Plasma enhancement Tetraethylorthosilicate Undoped Silicate Glass)등으로 이루어지며, 상기 제 2 층간 절연막(27)은 0.1μm 정도의 두께를 가지는 O3-TEOS USG 또는 P-SiH4USG(Plasma enhancement Silane Undoped Silicate Glass)등으로 이루어진다.2 (a) to (d) are manufacturing process diagrams showing a method for forming an interlayer insulating film according to the present invention. In the second (a) and (b), the first conductive semiconductor substrate 15 having the gate oxide film 17, the gate oxide film 19, and the gate 23 surrounded by the high temperature oxide film 21 is formed. A first interlayer insulating film 25 and a second interlayer insulating film 27 are sequentially formed on the upper surface of the first interlayer insulating film 25. The first interlayer insulating film 25 has a high temperature oxide (HTO: High Temperature Oxide) having a thickness of about 0.1 μm, O 3 -TEOS PSG (O 3 -Tetraethylorthosilicate Phospho-Silicate-Glass), O 3 -TEOS BPSG or P-TEOS USG (Plasma enhancement Tetraethylorthosilicate Undoped Silicate Glass) and the like, the second interlayer insulating film 27 is 0.1 It is composed of O 3 -TEOS USG or P-SiH 4 USG (Plasma enhancement Silane Undoped Silicate Glass) having a thickness of about μm.

상기 제 2(b)(c)에서 상기 기판(15)상면에 스핀-온-글래스(Spin On Galss : SOG)막(29)을 도포한다. 상기 스핀-온-글래스막 도포시 게이트간의 피치(pich)가 좁은 영역과 넓은 영역에서의 스핀-온-글래스막 두께 차이를 최대한 감소시키기 위하여 낮은 스핀 속도로 공정을 진행한다. 본 발명의 실시예에서는 1000RPM에서 2000RPM으로 한다. 그다음 열처리 공정을 실시하여 스핀-온-글래스막을 경화시킨다.A spin-on-glass (SOG) film 29 is coated on the upper surface of the substrate 15 in the second (b) and (c). When the spin-on-glass film is applied, the process is performed at a low spin speed in order to minimize the difference in the thickness of the spin-on-glass film in the narrow and wide regions between gates. In an embodiment of the present invention, 1000 RPM to 2000 RPM. Then, a heat treatment process is performed to cure the spin-on-glass film.

상기 제 2(c) 도에서 상기 게이트(23) 상면의 스핀-온-글래스막과 제 2 층간 절연막(27)이 완전히 제거될때까지 에치백 공정을 실시한다. 그 결과 상기 게이트 상부에 해당하는 영역에는 상기 제 1 층간 절연막(25)이 노출된다.In FIG. 2C, an etch back process is performed until the spin-on-glass film and the second interlayer insulating film 27 on the upper surface of the gate 23 are completely removed. As a result, the first interlayer insulating layer 25 is exposed in a region corresponding to the upper portion of the gate.

상기 제 2(d) 도에서 수초간 100 : 1HF 습식식각을 실시하여 상기 기판(15) 상면에 잔류된 스핀-온-글래스막(29)을 제거한다. 그 다음 상기 제 1 층간 절연막(25)상에서는 성장속도가 느리고 상기 제 2 층간 절연막(27)상에서는 성장속도가 빠른 제 3 층간 절연막(30)을 400℃ 정도의 온도에서 증착한다. 상기 제 3 층간 절연막(30)은 상기 게이트 상부에서 0.3μm 정도의 두께를 가지는 O3-TEOS USG막으로 한다. 그후 질소분위기에서 800℃ 정도의 온도로 30분정도 열처리를 실시하여 상기 제 3층간 절연막(30)을 경화시켜 층간 절연막의 평탄화 공정을 완료한다.In FIG. 2 (d), the spin-on-glass film 29 remaining on the upper surface of the substrate 15 is removed by wet etching 100: 1 HF for several seconds. The third interlayer insulating film 30 is then deposited at a temperature of about 400 ° C. on the first interlayer insulating film 25 and at a slow growth rate on the second interlayer insulating film 27. The third interlayer insulating film 30 is an O 3 -TEOS USG film having a thickness of about 0.3 μm above the gate. Thereafter, heat treatment is performed at a temperature of about 800 ° C. for about 30 minutes in a nitrogen atmosphere to cure the third interlayer insulating film 30 to complete the planarization of the interlayer insulating film.

상술한 바와 같이 본 발명은 반도체 장치의 층간 절연막 형성방법에 있어서, 기판상에 제 1 및 제 2 층간 절연막을 선택적으로 형성한 후 상기 각 층간 절연막 상에서 서로 다른 성장속도를 갖는 제 3 층간 절연막을 형성함에 의해 층간 절연막의 평탄화를 용이하게 구현할 수 이는 효과가 있다.As described above, in the method of forming an interlayer insulating film of a semiconductor device, after forming the first and second interlayer insulating films on a substrate, a third interlayer insulating film having a different growth rate is formed on each of the interlayer insulating films. By this, the planarization of the interlayer insulating film can be easily realized, which is advantageous.

또한 종래의 BPSG막 대신 USG막을 층간 절연막으로 사용하였기 때문에 층간 절연막에 함유된 불순물이 트랜지스터에 영향을 미치는 현상을 제거할 수 있는 효과도 있다.In addition, since the USG film is used as the interlayer insulating film instead of the conventional BPSG film, it is possible to eliminate the phenomenon in which impurities contained in the interlayer insulating film affect the transistor.

Claims (8)

소정 도전형의 반도체 기판상의 소정영역 도전층 패턴이 형성된 반도체 장치의 층간 절연막 형성방법에 있어서, 상기 기판 상부에 제 1 층간 절연막과 제 2 층간 절연막을 순차적으로 형성하는 제 1 공정과, 상기 기판 상면에 절연막을 형성한 후 상기 도전층 상부의 제 1 층간 절연막의 표면이 노출될때까지 에치백 공정을 실시하는 제 2 공정과, 상기 제 2 공정에 의해 기판상에 잔류된 상기 절연막을 제거한 후, 상기 제 1 층간 절연막상에서 제 1 속도로 성장되고 상기 제 2 층간 절연막상에서 상기 제 1 속도보다 빠른 제 2 속도로 성장되는 제 3 층간 절연막을 형성하는 제 3 공정이 순차적으로 이루어지는 공정을 구비함을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.A method of forming an interlayer insulating film of a semiconductor device, in which a predetermined region conductive layer pattern is formed on a semiconductor substrate of a predetermined conductivity type, comprising: a first step of sequentially forming a first interlayer insulating film and a second interlayer insulating film on the substrate; A second step of performing an etch-back process until the surface of the first interlayer insulating film over the conductive layer is exposed after the insulating film is formed on the conductive layer; and after removing the insulating film remaining on the substrate by the second step, And a third step of sequentially forming a third interlayer insulating film grown on the first interlayer insulating film at a first rate and growing on the second interlayer insulating film at a second rate faster than the first rate. An interlayer insulating film forming method of a semiconductor device. 제 1 항에 있어서, 상기 제 1 층간 절연막이 고온산화막(HTO : High Tempe rature Oxide) P-TEOS, O3-TEOS, BPSG, 또는 O3-TEOS PSG 등임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The interlayer insulating film of claim 1, wherein the first interlayer insulating film is a high temperature oxide film (HTO) P-TEOS, O 3 -TEOS, BPSG, or O 3 -TEOS PSG. Way. 제 2 항에 있어서, 상기 제 2 층간 절연막이 O3-TEOS USG, P-SiH4USG등임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of claim 2, wherein the second insulating interlayer is O 3 -TEOS USG, P-SiH 4 USG, or the like. 제 3 항에 있어서, 상기 제 3 층간 절연막이 USG막임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.4. The method for forming an interlayer insulating film of a semiconductor device according to claim 3, wherein said third interlayer insulating film is a USG film. 제 1 항에 있어서, 상기 절연막이 스핀-온-글래스막 임을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein said insulating film is a spin-on-glass film. 제 5 항에 있어서, 상기 스핀-온-글래스막이 1000RPM에서 2000RPM 정도의 스핀 속도로 도포됨을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of claim 5, wherein the spin-on-glass film is applied at a spin speed of about 1000 RPM to about 2000 RPM. 제 1 항에 있어서, 상기 제 3 공정후 소정 온도에서 상기 제 3 절연막을 열처리하는 공정을 더 구비함을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.The method of forming an interlayer insulating film of a semiconductor device according to claim 1, further comprising a step of heat-treating the third insulating film at a predetermined temperature after the third step. 제 7 항에 있어서, 상기 열처리가 800℃ 정도의 온도에서 실시됨을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.8. The method for forming an interlayer insulating film of a semiconductor device according to claim 7, wherein said heat treatment is performed at a temperature of about 800 deg.
KR1019910016413A 1991-09-19 1991-09-19 Inter-layer insulating film depositing method KR950000854B1 (en)

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