KR0141932B1 - Method of manufacture in semiconductor device - Google Patents

Method of manufacture in semiconductor device

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Publication number
KR0141932B1
KR0141932B1 KR1019940026836A KR19940026836A KR0141932B1 KR 0141932 B1 KR0141932 B1 KR 0141932B1 KR 1019940026836 A KR1019940026836 A KR 1019940026836A KR 19940026836 A KR19940026836 A KR 19940026836A KR 0141932 B1 KR0141932 B1 KR 0141932B1
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KR
South Korea
Prior art keywords
layer
forming
barrier layer
insulating film
semiconductor device
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KR1019940026836A
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Korean (ko)
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KR960015731A (en
Inventor
라관구
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문정환
엘지반도체주식회사
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Priority to KR1019940026836A priority Critical patent/KR0141932B1/en
Publication of KR960015731A publication Critical patent/KR960015731A/en
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Publication of KR0141932B1 publication Critical patent/KR0141932B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 반도체기판 위에 산화막을 형성하는 공정과, 상기 산화막 위에 구리를 증착시켜 금속층을 형성하는 공정과, 상기 금속층을 사진식각법으로 패터닝한 후 결과물 전면에 HMDS와 같은 유기실란을 도포하여 장벽층을 형성하는 공정과, 상기 장벽층 위에 SOG를 도포하여 절연막을 형성하는 공정과, 상기 절연막 위에 표면안정화층을 형성하는 공정을 포함하여 구성되며, 상기 장벽층과 절연막이 구리가 다른막으로 침투하는 것을 방지하여 0.3μm이하의 미세패턴배선의 제작을 용이하게 하며, 사진식각법을 종래보다 감소시켜 제조가를 감소 및 양품률을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: forming an oxide film on a semiconductor substrate; depositing copper on the oxide film to form a metal layer; and patterning the metal layer by photolithography, followed by HMDS on the entire surface of the resultant product. Forming a barrier layer by applying an organic silane, a process of forming an insulating film by applying SOG on the barrier layer, and forming a surface stabilization layer on the insulating film. The insulating film prevents copper from penetrating into another film, thereby facilitating the fabrication of fine pattern wiring of 0.3 μm or less, and reducing the photolithography method compared to the conventional method, thereby reducing the manufacturing cost and improving the yield.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

제1도는 종래의 기술에 의한 반도체장치의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

제2도는 본 발명에 의한 반도체장치의 제조방법을 도시한 단면도.2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11:반도체기판 13:산화막11: Semiconductor substrate 13: Oxide film

15:금속층 17:장벽층15: metal layer 17: barrier layer

19:절연막 21:표면안정화층19: insulating film 21: surface stabilization layer

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 금속배선공정을 개선하기 위한 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving a metal wiring process.

일반적으로 반도체장치는 배선금속박막으로서 n+ 실리콘 및 p+ 실리콘에 대한 접촉저항이 낮고 성막·가공이 용이하여 알루미늄(Al)이 주로 사용되어왔는데, 최근에는 서브마이크론 폭의 미세배선이 일반화되면서 첫째, 전자의 흐름에 의한 알루미늄 원자의 확산이나 활성화 에너지가 낮은 입계(粒界)확산, 그리고 결정입자직경 및 방위의 불균일로 인해 전류밀도가 증가하여 일렉트로 마이그레이션 현상이 발생하여 배선수명이 저하되며, 둘째, 가열시의 압축응력과 낮은 재결정온도로 인해 필로크가 성장하여 층간절연내압이 불량하게 되며, 세째, 표면안정화(passivation)층에서 받는 인장응력에 의해 배선이 단선되거나 부분적으로 손실되는 등 여러가지 원인들에 의해 신뢰성이 저하되는 등 많은 문제점들 때문에 다른 대체금속물질을 개발하기 위한 많은 연구가 진행되고 있다.In general, semiconductor devices have mainly used aluminum (Al) because they have low contact resistance to n + silicon and p + silicon and are easy to form and fabricate as a wiring metal thin film. Due to the diffusion of aluminum atoms or the grain boundary diffusion with low activation energy, and the unevenness of crystal grain diameter and orientation, the current density increases, resulting in electromigration phenomenon. The compressive stress and low recrystallization temperature at the time of the growth of the pill due to poor interlayer dielectric breakdown voltage, and third, due to various stresses such as wire disconnection or partial loss due to tensile stress received from the surface passivation layer. To develop other alternative metal materials due to many problems Many studies are in progress.

이러한 연구중의 하나로서 전기 전도도의 증가와 일렉트로마이그레이션(electormigration) 저항성 향상을 위해 구리(Cu)를 배선금속을 사용하는 방법이 있는데, 제1도를 참조하여 이를 개략적으로 설명하면 다음과 같다.One of such studies is a method of using copper (Cu) wiring metal to increase electrical conductivity and improve electromigration resistance. Referring to FIG. 1, the schematic description is as follows.

먼저 (a)도 및 (b)도에서 반도체기판(1)상에 산화막(3)을 소정의 두깨로 형성한 후 상기 산화막(3) 위에 구리를 증착시켜 금속층(5)을 형성한다.First, an oxide film 3 is formed on the semiconductor substrate 1 with a predetermined thickness in FIGS. 1A and 2B, and copper is deposited on the oxide film 3 to form a metal layer 5.

이어서 (c)도 내지 (e)도에서 상기 금속층(5) 위에 포토레지스터를 도포, 노광 및 현상하여 사진식각 마스크를 형성하고 이를 적용하여 상기 금속층(5)을 식각한 후 상기 사진식각 마스크를 제거하며, 계속하여 상기 결과물 위에 TiW나 Cr 또는 Al을 증착시킨 후 다시 사진식각 마스크를 형성하고 이를 적용하여 장벽층(7)을 형성한다.Subsequently, in (c) to (e), a photoresist is applied, exposed, and developed on the metal layer 5 to form a photolithography mask, and then the photoresist is etched to remove the photolithography mask. Subsequently, after depositing TiW, Cr or Al on the resultant to form a photo-etch mask and applying it again to form a barrier layer (7).

여기서 상기 장벽층(7)은 현재의 식각기술로는 구리에 대한 식각률이 너무 늦어 구리가 빠른 시간안에 산화되기 쉽고 후속공정시 형성되는 표면안정화층(9)로 확산되는 등의 문제점을 방지하기 위한 것이다.Wherein the barrier layer (7) is to prevent the problem such as diffusion of the surface stabilization layer (9) is formed in a subsequent process is easy to oxidize in a fast time because the etching rate for copper is too late in the current etching technology will be.

마지막으로 (f)도에서는 결과물의 표면을 평탄화시키기 위해 상기 장벽층(7)이 식각된 결과물 위해 소정의 두께로 표면안정화층(9)을 형성한다.Finally, in (f), the surface stabilization layer 9 is formed to a predetermined thickness for the resultant product of which the barrier layer 7 is etched to planarize the surface of the resultant product.

그러나 상기와 같은 종래의 방법은 사진식각공정이 2회실시되어야 하며, 상기 장벽층을 형성하기 위해 TiW나 Cr 또는 Al을 사용함에 따라 공정이 복잡할뿐만 아니라 제조가가 높아져 가격경쟁력을 떨어뜨리며, 타켓(target)사용에 의한 입자증가로 인해 양품률이 저하되는 문제점이 있다.However, the conventional method as described above should be performed twice the photolithography process, the use of TiW, Cr or Al to form the barrier layer is not only complicated, but also increases the manufacturing cost and lowers the price competitiveness, There is a problem that the yield is lowered due to the increase in particles by the use of the target (target).

따라서 본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 유기실란으로 장벽층을 형성하고, 그 위에 SOG 로 절연막을 형성하여 사진식가공정을 줄이고, 상기 유기실란으로된 장벽층과 절연막에 의해 구리가 다른막으로 침투하는 것을 방지함으로써 0.3μm이하의 미세패턴배선의 제작이 용이하며, 제조가를 감소시키고 양품들을 향상시킬 수 있는 반도체장치 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to form a barrier layer with an organic silane, and to form an insulating film with SOG thereon to reduce the photo-eating process to solve the above problems, the copper layer by the barrier layer and the insulating film made of the organic silane By preventing penetration into other films, it is easy to manufacture fine pattern wirings of 0.3 μm or less, and to provide a semiconductor device manufacturing method that can reduce manufacturing costs and improve quality products.

상기 목적을 달성하기 위한 본 발명의 반도체장치의 제조방법은 반도체기판 위에 산화막을 형성하는 공정과, 상기 산화막 위에 구리를 증차시켜 금속층을 형성하는 공정과, 상기 금속층을 사진식각법으로 패터닝한 후 결과를 전면에 유기실란을 도포하여 장벽층을 형성하는 공정과, 상기 장벽층 위에 상기 장벽층 위에 절연물질을 도포하여 절연막을 형성하는 공정과, 상기 절연막 위에 표면안정화층을 형성하는 공정을 포함하여 구성된 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an oxide film on a semiconductor substrate, forming a metal layer by adding copper on the oxide film, and patterning the metal layer by photolithography. Forming a barrier layer by coating an organosilane on the entire surface, forming an insulating film by applying an insulating material on the barrier layer on the barrier layer, and forming a surface stabilization layer on the insulating film. It is characterized by.

이하 첨부도면을 참조하여 본 발명을 좀 더 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

본 발명의 반도체장치의 제조방법은 제2도에 도시한 바와 같이 먼저 (a)도 및 (b)도에서 반도체기판(11) 위헤 소정의 두께로 산화막(SiO2)(13)을 형성한 후 상기 산화막(13)의 위에 구리를 소정의 두께로 증착시켜 금속층(15)을 형성하며, (c)도에서는 상기 금속층(15) 위에 포토레지스트를 도포, 노광 및 현상하여 사진식각마스크를 형성하고 이를 적용하여 상기 금속층(15)을 식각한 후 원하는 패턴이 완성되면 상기 사진식각마스크를 제거한다.In the method of manufacturing a semiconductor device of the present invention, as shown in FIG. 2, first, an oxide film (SiO 2 ) 13 is formed on the semiconductor substrate 11 at a predetermined thickness in FIGS. A copper layer is deposited on the oxide layer 13 to a predetermined thickness to form a metal layer 15. In FIG. 3C, a photoresist is applied, exposed, and developed on the metal layer 15 to form a photolithography mask. After etching the metal layer 15 by applying to remove the photo etching mask when the desired pattern is completed.

이어서, (d)도에서 상기 사진식각마스크 제거 후 결과물 위에 상기 구리가 다른막, 예를들면 표면안정화층(21)으로 침투하는 것을 방지하기 위해 유기실란의 일종인 HMDS(Hexa Methyl Disilazane)를 1 μm 이하의 두께로 도포하고 500℃ 이하에서 의 열처리(bake) 과정을 거쳐 장벽층(7)을 형성하며, (e)도에서 상기 장벽층(17) 위에 인이 도핑된 SOG를 2μm 이하의 두께로 도포하고 상기 장벽층(17)과 동일하게 500℃ 이하에서 의열처리하여 절연막(19)을 형성한 다음 (f)도에서 상기 절연막(19) 위에 표면을 평탄화시키기 위한 표면안정화층(21)을 형성한다.Subsequently, in order to prevent the copper from penetrating into another film, for example, the surface stabilization layer 21, the HMDS (Hexa Methyl Disilazane), which is a kind of organosilane, is added to the resultant after removing the photolithography mask. A barrier layer 7 is formed by applying a thickness of less than or equal to μm and undergoing a heat treatment at 500 ° C. or less, and in (e), a SOG doped with phosphorus on the barrier layer 17 is less than or equal to 2 μm. And a heat treatment at 500 ° C. or lower in the same manner as the barrier layer 17 to form an insulating film 19, and then, in (f), a surface stabilization layer 21 for planarizing the surface of the insulating film 19 is formed. Form.

이때 상기 SOG로된 절연막(19)은 상기 금속층(15)의 패턴간에 채워지게 됨으로써 평탄화를 용이하게 실현할 수 있도록 하며, 상기 장벽층(17)가 함께 구리가 다른 막으로 확산되는 것을 방지한다.In this case, the insulating film 19 made of SOG is filled between the patterns of the metal layer 15 so that the planarization can be easily realized, and the barrier layer 17 is prevented from spreading copper together to another film.

이상에서와 같이 본 발명에 의하면 유기실란으로 사진식가공정없이 장벽층을 형성하고 그 위에 SOG로 절연막을 형성함으로써 구리가 다른막으로 침투하는 것을 방지하고, 이에 따라 0.3μm이하의 미세패턴배선이 제작을 용이하게 하며, 상기와 같은 사진식가공정을 종래보다 감소시켜 용이하며, 제조가를 감소 및 양품들을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, by forming a barrier layer with an organic silane without a photolithography process and forming an insulating film with SOG thereon, copper is prevented from penetrating into another layer, and thus, fine pattern wiring of 0.3 μm or less is produced. And it is easy to reduce the above-described photo-education process than the conventional, there is an effect that can reduce the manufacturing cost and improve the good quality.

Claims (7)

반도체기판 위에 산화막을 형성하는 공정과, 상기 산화막 위에 구리를 증착시켜 금속층을 형성하는 공정과, 상기 금속층을 사진식각법으로 패터닝한 후 결과물 전면에 유기실란을 도포하여 장벽층을 형성하는 공정과, 상기 장벽층 위에 절연물질을 도포하여 절연막을 형성하는 공정과, 상기 절연막 위에 표면안정화층을 형성하는 공정을 포함하여 구성된 것을 특징으로 하는 반도체장치의 제조방법.Forming an oxide film on a semiconductor substrate, depositing copper on the oxide film to form a metal layer, patterning the metal layer by photolithography, and then applying an organic silane to the entire surface of the resultant to form a barrier layer; And forming an insulating film by applying an insulating material on the barrier layer, and forming a surface stabilization layer on the insulating film. 제1항에 있어서, 상기 유기실란은 HMDS임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the organosilane is HMDS. 제1항에 있어서, 상기 장벽층은 두께가 1μm 이하임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the barrier layer has a thickness of 1 μm or less. 제1항에 있어서, 상기 절연막은 P가 20 wt% 이하 도핑된 SOG임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the insulating layer is SOG doped with P of 20 wt% or less. 제1항에 있어서, 상기 절연막은 두께가 2μm 이하임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the insulating layer has a thickness of 2 μm or less. 제2항에 있어서, 상기 HMDS 500℃ 이하의 열처리공정을 거쳐 형성됨을 특징으로 하는 반도체장치의 제조방법.The method of claim 2, wherein the semiconductor device is formed through a heat treatment of 500 ° C. or less. 제4항에 있어서, 상기 SOG 500℃ 이하의 열처리공정을 거쳐 형성됨을 특징으로 하는 반도체장치 제조방법.The method of claim 4, wherein the semiconductor device is formed through a heat treatment of 500 ° C. or less.
KR1019940026836A 1994-10-20 1994-10-20 Method of manufacture in semiconductor device KR0141932B1 (en)

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