KR100754757B1 - Method for multilevel copper interconnects for ultra large scale integration - Google Patents
Method for multilevel copper interconnects for ultra large scale integration Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000010949 copper Substances 0.000 title claims description 57
- 229910052802 copper Inorganic materials 0.000 title claims description 52
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims description 51
- 230000010354 integration Effects 0.000 title description 2
- 239000002184 metal Substances 0.000 claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 claims abstract description 80
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 150000004706 metal oxides Chemical class 0.000 claims abstract 73
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical group [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 42
- 239000005751 Copper oxide Substances 0.000 claims description 36
- 229910000431 copper oxide Inorganic materials 0.000 claims description 36
- 238000000151 deposition Methods 0.000 claims description 32
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 8
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- HBEQXAKJSGXAIQ-UHFFFAOYSA-N oxopalladium Chemical group [Pd]=O HBEQXAKJSGXAIQ-UHFFFAOYSA-N 0.000 claims 6
- MUMZUERVLWJKNR-UHFFFAOYSA-N oxoplatinum Chemical group [Pt]=O MUMZUERVLWJKNR-UHFFFAOYSA-N 0.000 claims 6
- 229910003445 palladium oxide Inorganic materials 0.000 claims 6
- 229910003446 platinum oxide Inorganic materials 0.000 claims 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 238000007772 electroless plating Methods 0.000 abstract description 6
- 238000001459 lithography Methods 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 2
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- 239000010409 thin film Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 238000007540 photo-reduction reaction Methods 0.000 description 4
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- 238000004549 pulsed laser deposition Methods 0.000 description 3
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- QNZRVYCYEMYQMD-UHFFFAOYSA-N copper;pentane-2,4-dione Chemical compound [Cu].CC(=O)CC(C)=O QNZRVYCYEMYQMD-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
집적 회로들에서 다층 상호접속 구조들을 확립하기 위해 얇은 금속 산화물막(220)을 시드층으로서 사용하여 집적 회로들을 제조하는 방법이 제공된다. 얇은 층의 금속 산화물막(220)은 웨이퍼(210) 상에 침착되고, 금속 라인 패턴(215)에 대응하는 패턴으로 금속 산화물막(220)을 노출하기 위해 표준 광학 리소그래피(standard optical lithography)가 사용된다. 금속 산화물막(220)은 금속층(240)으로 변환되고, 금속막(250)은 변환된 산화물막(260) 상에 선택적인 CVD 또는 무전해 도금(electroless plating)에 의해 침착될 수 있다. 그 다음, 비아 홀들(280)이 유사한 공정에서 비아 홀 리소그래피를 사용하여 제조된다. 상기 공정은 소망의 다층 구조가 제조될 때까지 계속된다.A method of fabricating integrated circuits is provided using a thin metal oxide film 220 as a seed layer to establish multilayer interconnect structures in integrated circuits. A thin layer of metal oxide film 220 is deposited on wafer 210 and standard optical lithography is used to expose metal oxide film 220 in a pattern corresponding to metal line pattern 215. do. The metal oxide film 220 is converted into the metal layer 240, and the metal film 250 may be deposited on the converted oxide film 260 by selective CVD or electroless plating. Via holes 280 are then fabricated using via hole lithography in a similar process. The process continues until the desired multilayer structure is produced.
비아 홀 리소그래피, 산화물막, 시드층, 화학 기계적 연마, 포토레지스트층Via Hole Lithography, Oxide Film, Seed Layer, Chemical Mechanical Polishing, Photoresist Layer
Description
본 발명은 집적 회로의 제조에 관한 것이다. 특히, 본 발명은 집적 회로에서의 다층 상호접속 구조들을 확립하기 위해 얇은 구리 산화물 막을 시드층(seed layer)으로서 이용하는 것에 관한 것이다.The present invention relates to the manufacture of integrated circuits. In particular, the present invention relates to the use of thin copper oxide films as seed layers to establish multilayer interconnect structures in integrated circuits.
집적 회로들(IC)의 소형화의 급속한 발달은 지금까지 증가하는 성능에서의 보다 조밀하고 보다 미세하게 피치된 칩들을 야기한다. 진보한 IC들의 성능을 향상시키기 위하여, 상호접속 시스템들은 서서히 알루미늄 박막들로부터 구리 박막들로 옮겨가고 있다. 전통적으로 사용되는 재료인 알루미늄과 비교해서, 구리는 집적 회로 성능을 향상시키는데 있어서 중요한 보다 많은 이점들을 갖는다. 첫째, 구리는 알루미늄보다 훨씬 낮은 시트 저항(sheet resistivity)을 갖는다. 따라서, 같은 전류량을 운반하는데 있어서, 구리 라인은 알루미늄 라인보다 더 좁고 더 얇게 만들어질 수 있다. 그러므로, 구리 라인의 사용은 보다 높은 집적 밀도를 고려하게 한다. 또한, 보다 좁고 보다 얇은 도전 라인들은 레벨간 및 라인간 용량 양쪽을 감소시키고, 이는 회로에 대하여 보다 고속이고 보다 적은 방출을 야기시킨다. 마지막으로, 구리는 알루미늄보다 양호한 전자이동 저항(electromigration resistance)을 갖는다. 따라서, 금속 라인들이 보다 얇게 만들어지고, 회로가 보다 조밀하게 패키징되어 있기 때문에, 구리는 IC들에 사용될 때 보다 높은 신뢰성을 제공한다.The rapid development of miniaturization of integrated circuits (IC) results in denser and finer pitched chips in ever increasing performance. To improve the performance of advanced ICs, interconnect systems are slowly moving from aluminum thin films to copper thin films. Compared to aluminum, which is a traditionally used material, copper has many more important advantages in improving integrated circuit performance. First, copper has much lower sheet resistivity than aluminum. Thus, in carrying the same amount of current, the copper line can be made narrower and thinner than the aluminum line. Therefore, the use of copper lines allows to consider higher integration densities. In addition, narrower and thinner conductive lines reduce both interlevel and interline capacitance, which results in faster and less emissions for the circuit. Finally, copper has better electromigration resistance than aluminum. Thus, since metal lines are made thinner and the circuit is more densely packaged, copper provides higher reliability when used in ICs.
구리 상호접속들을 제조하기 위해 제안된 여러 방법들 중에서, 가장 유망한 방법은 다마신 공정(Damascene process)이라고 생각된다. 이 방법을 이용할 때에, 트렌치들 및 비아들은 블랭킷 유전체들(blanket dielectrics)에서 형성되고, 이어서 금속은 불필요한 표면 금속을 제거하기 위해 화학 기계적 연마(CMP; chemical mechanical planarization)에 따르는 하나의 단계에서 트렌치들 및 홀들에 침착된다. 이로 인해 트렌치들 및 홀들 내의 소망의 금속과, 후속 처리를 위해 평탄화된 표면이 남겨진다.Among the various methods proposed for manufacturing copper interconnects, the most promising method is considered to be the damascene process. When using this method, trenches and vias are formed in blanket dielectrics, and the metal is then trenched in one step following chemical mechanical planarization (CMP) to remove unwanted surface metals. And in the holes. This leaves the desired metal in the trenches and holes and a flattened surface for subsequent processing.
그러나, 특히 비아들을 위한 전술한 CMP 공정 동안에, 침착된 구리의 99% 이상이 제거된다. 구리 단독의 관점에서, 이것은 매우 비경제적이고 고비용이 든다. 게다가, 패드들 및 슬러리들(slurrys)과 같은 소비재들을 제조하는 것은 CMP 공정 동안에 과도하게 소모된다. 이 부산물 제조의 처리는 보다 실행가능한 방법을 보상하기 위해 충분한 환경적인 관심이다. 따라서, CMP 없이도 구리 금속화를 달성하는 것이 가장 바람직하다. 무전해 도금(electroless plating) 또는 화학 기상 침착(CVD; chemical vaporization deposition)에 의한 선택적인 구리 침착은 "CMP 없는(CMP-less)" 금속화 기술을 제공한다. 예를 들어, 무전해 선택적으로 침착된 구리를 사용하여 다층 상호접속 구조들을 제조하는 하나의 이러한 방법은, 이전에 동시 계류중인 출원 "ULSI를 위한 선택적인 무전해 도금 다층 구리 금속화(A SELECTIVE ELECTROLESS-PLATED MULTILAYER COPPER METALLIZATION FOR ULSI)" 제목의 마이크론 도켓 제99-0715호에 기술되어 있으며, 이는 참조로서 본원에 합체된다. 그 방법에서, Pd 또는 Cu의 매우 얇은 막은 3 내지 10 nm의 두께 범위에서 "섬모양의 구조(island structure)" 또는 가까스로 연속적인 박막을 형성한다.However, at least 99% of the deposited copper is removed, especially during the CMP process described above for vias. In terms of copper alone, this is very uneconomical and expensive. In addition, manufacturing consumer products such as pads and slurries is excessively consumed during the CMP process. The treatment of this by-product preparation is of sufficient environmental interest to compensate for a more viable method. Therefore, it is most desirable to achieve copper metallization without CMP. Selective copper deposition by electroless plating or chemical vapor deposition (CVD) provides a "CMP-less" metallization technique. For example, one such method of fabricating multilayer interconnect structures using electrolessly selectively deposited copper has previously been described in the co-pending application “Selective Electroless Plating Multilayer Copper Metallization for ULSI. -PLATED MULTILAYER COPPER METALLIZATION FOR ULSI. ", Incorporated herein by reference. In that method, a very thin film of Pd or Cu forms a continuous thin film "island structure" or barely in the thickness range of 3 to 10 nm.
본 발명의 한 양상에서, 금속 라인들 및 비아 홀들을 포함하는 다층 구리 상호접속들은 웨이퍼 상에 제조된다. 처음에, 구리 산화물의 얇은 시드층이 웨이퍼 상에 침착된다. 표준 광학 리소그래피(standard optical lithography)에 의해 금속 라인 패턴을 규정한 후, 노출된 구리 산화물은 자외선 포토 감소법(ultra-violet photo reduction method)을 사용하여 구리로 변환된다. 그 후, 구리막은 무전해 도금 또는 화학 기상 침착(CVD)을 사용하여 침착되고, 그에 의해 평면 표면이 제공된다. 다음 단계에서, 비아 홀들은 비아 홀 리소그래피(via hole lithography)와 같은 전형적인 방법들을 사용하여 제조되고, 구리 산화물의 제 2 층은 제 1 층과 유사한 방법으로 침착된다. 제 1 구리층과 같이, 평면 표면이 후속 층들을 위해 제공된다.In one aspect of the invention, multilayer copper interconnects comprising metal lines and via holes are fabricated on a wafer. Initially, a thin seed layer of copper oxide is deposited on the wafer. After defining the metal line pattern by standard optical lithography, the exposed copper oxide is converted to copper using an ultraviolet-violet photo reduction method. The copper film is then deposited using electroless plating or chemical vapor deposition (CVD), thereby providing a planar surface. In the next step, via holes are made using typical methods such as via hole lithography, and a second layer of copper oxide is deposited in a similar way as the first layer. Like the first copper layer, a planar surface is provided for subsequent layers.
결과로서, 바람직한 많은 금속층들을 갖는 다층 상호접속 구조들은 CMP를 필요로 하지 않고도 상기 공정을 반복함으로써 제조될 수 있다. 시드층으로서 구리를 대신하여 구리 산화물을 사용하는 것의 한가지 중요한 이점으로는 IC들에 있어서의 잠재적으로 높은 제조 수율이다. 순수 구리 시드층이 사용되면, 천연 구리 산화물은 얼마나 웨이퍼가 공기에 노출되는지에 근거하여 웨이퍼의 표면 상에 형성될 수 있다. 구리 산화물을 제거하는 부가의 단계를 실행하지 않는다면 재현성이 문제가 된다.As a result, multilayer interconnect structures with many desirable metal layers can be produced by repeating the process without the need for CMP. One important advantage of using copper oxide in place of copper as the seed layer is the potentially high manufacturing yield in ICs. If a pure copper seed layer is used, natural copper oxide can be formed on the surface of the wafer based on how the wafer is exposed to air. Reproducibility is a problem unless additional steps are taken to remove the copper oxide.
도 1 내지 도 5는 초대규모 집적회로를 위한 다층 금속 상호접속들을 제조하는 예시적인 방법을 도시하는 단면도.1-5 are cross-sectional views illustrating an exemplary method of fabricating multilayer metal interconnections for ultra-scale integrated circuits.
도 6은 본 발명의 대안적인 실시예의 단면도.6 is a cross-sectional view of an alternative embodiment of the present invention.
본 발명의 예시적인 방법에 따라서, 초대규모 집적회로(ULSI)를 위해 다층 구리 상호접속들을 제조하는 방법이 설명된다. 소망의 다층 상호접속 구조를 제조하기 위하여 얇은 구리 산화물 막을 시드층으로서 사용하는 것이 제공된다. 이전에 구리 산화물을 시드층으로서 사용하는 무전해로 침착된 구리 라인들의 제조는, 공동 양도된 특허출원 "도전성 재료 패터닝 방법(CONDUCTIVE MATERIAL PATTERNING METHODS)" 제목의 마이크론 도켓 제99-0671호 및 "집적된 상호접속들로부터 구리 산화물의 제거(REMOVAL OF COPPER OXIDES FROM INTEGRATED INTERCONNECTS)" 제목의 미국 특허출원 제09/484,683호에 기술되어 있으며, 이는 참조로서 본원에 합체된다. In accordance with an exemplary method of the present invention, a method of manufacturing multilayer copper interconnects for ultra-scale integrated circuits (ULSI) is described. It is provided to use a thin copper oxide film as seed layer to produce the desired multilayer interconnect structure. The preparation of electrolessly deposited copper lines, previously using copper oxide as seed layer, is described in Micron-Dock No. 99-0671 and "Integrated" under the co-transferred patent application "CONDUCTIVE MATERIAL PATTERNING METHODS." US Patent Application No. 09 / 484,683 entitled "REMOVAL OF COPPER OXIDES FROM INTEGRATED INTERCONNECTS", which is incorporated herein by reference.
본 발명의 개념들을 제한하는 것이 아니라 단지 예시하고 가르치기 위하여 제공되는 실시예들은, 본 기술분야의 숙련된 자들이 본 발명을 이행하거나 실행하는데 충분히 상세하게 도시되고 기재되어 있다. 따라서, 본 발명의 불명료함을 회피하기 위해 적절한 데에, 명세서는 본 기술분야의 숙련된 자들에게 알려진 어떤 정보를 생략할 수도 있다. The embodiments, which are provided to illustrate and teach, but not to limit the concepts of the invention, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Accordingly, the specification may omit any information known to those skilled in the art, where appropriate, to avoid obscuring the present invention.
도 1 내지 도 5는 USLI를 위해 다층 상호접속들을 제조하는 예시적인 방법을 집합적으로 연속하여 설명하는 다수의 단면도들을 도시한다. 도 1에 도시된 바와 같이, 상기 방법은 반도체 웨이퍼(210)를 사용하여 시작한다. 반도체 웨이퍼(210)가 제조의 임의의 스테이지에 있을 수도 있다는 것을 이해할 수 있다. 10 내지 30 nm의 두께 범위에서, 구리 산화물의 얇은 층(220)은 반도체 웨이퍼(210)의 표면 상에 침착된다. 구리 및 구리 산화물이 다층 상호접속들을 제조하기 위하여 본원에 개시되어 있지만, 백금 및 팔라듐과 같은 다른 금속들과 그 산화물들이, 예컨대 개시된 발명에서 사용하는데 매우 적합하다는 것을 이해할 수 있다. 1-5 show a number of cross-sectional views that collectively describe in series an exemplary method of manufacturing multilayer interconnections for a USLI. As shown in FIG. 1, the method begins with a
예시적인 실시예에서, CVD, 이온화된 마그네트론 스퍼터링 기술, DC 마그네트론 자기 스퍼터링 기술(DC magnetron self-supttering technique), 플라즈마 증기, 플라즈마 CVD, 금속유기의 마이크로파 플라즈마 CVD, 구리 디피발로이메탄테(copper dipivaloymethanate)로부터의 CVD 및 펄스 레이저 침착을 포함하지만, 그에 제한되지 않은 여러 가지의 기술들이 구리 산화물층(220)을 침착하는데 사용될 수 있다.In an exemplary embodiment, CVD, ionized magnetron sputtering technology, DC magnetron self-supttering technique, plasma vapor, plasma CVD, metal organic microwave plasma CVD, copper dipivaloymethanate Various techniques can be used to deposit the
예를 들어, V.F.Drobny 등이 얇은 고체막(Thin Solid Films), Vol.61, No.1, 89 내지 98(1979)에 보고한 바와 따르면, 어떤 특성들의 범위를 갖는 얇은 구리 산화물 막들을 생성하는 산소 아르곤 혼합물들에서의 반응적인 스퍼터링은 방전내의 산소의 부분적인 압력을 변경함으로써 제어되며, 이는 참조로서 본원에 합체된다. 더 근래에, A.Parretta 등이 참조로서 본원에 합체되는 "물질 상태 고체 A(Physica Status Solidi A)", Vol.155, No.2, 399 내지 404(1996)에 보고한 바에 의하면, 반응적인 RF 마그네트론 스퍼터링에 의해 형성된 구리 산화물 막들의 전기 및 광학 특성들을 검토하여, 단일 현상 Cu2O 및 CuO가 산소의 부분 압력을 제어함으로써 얻어질 수 있다고 결론내려 있다. Parretta는 Cu2O 막들의 전형적인 저항력이 순수 구리보다 더 높은 크기의 적어도 6 차수인 43 옴 cm였음을 발견하였다.For example, as reported by Thin Solid Films, Vol. 61, No. 1, 89-98 (1979), VFDrobny et al., Produce oxygen that produces thin copper oxide films with a range of properties. Reactive sputtering in argon mixtures is controlled by changing the partial pressure of oxygen in the discharge, which is incorporated herein by reference. More recently, A. Parretta et al. Reported in "Physica Status Solidi A", Vol. 155, No. 2, 399-404 (1996), which is incorporated herein by reference. Examining the electrical and optical properties of the copper oxide films formed by RF magnetron sputtering, it is concluded that single development Cu 2 O and CuO can be obtained by controlling the partial pressure of oxygen. Parretta found that the typical resistivity of Cu 2 O films was 43 ohm cm, at least six orders of magnitude higher than pure copper.
다른 기술에서, K.Santra 등이 참조로서 본원에 합체되는 "얇은 고체막들(Thin Solid Fims)", Vol.213, No.2, 226 내지 9(1992)에 보고한 바에 따르면, 구리 산화물 막들은 일정한 산소 압력의 면전에서 플라즈마 방법을 통해 금속의 구리를 증발시킴으로서 기판들 상에 침착된다. "침착된 것만큼" 제 1 구리의 산화물은 위상이 어닐링 후 제 2 구리의 산화물로 변경된다. 또한, H.Holzsuch 등이 본원에 참조로서 합체되는 "응용 물질 A(Applied Physics A)", Vol.A51, No.6, 486 내지 90(1990)에 보고한 바에 따르면, 구리 산화물 막들은 전구체(precursor)로서 아세틸아세톤 구리를 사용한 CVD에 의해 침착된다. Holzsuch는 기판의 온도의 증가가 Cu2O + CuO 로부터 Cu 까지 침착의 위상들을 변경한다는 것을 발견하였다. 500℃보다 더 큰 온도에서, 침착 비율들은 높았지만, 막들은 주로 금속의 구리였다. 또한, B.Wisniesky 등이 본원에 참조로서 합체되는 "Journal de Physique", Vol.1, No.C2, 389 내지 95(1991)에 소개한 바에 따르면, 혁신적인 기술로서 마이크로파 CVD는 아세틸아세톤 구리의 휘발성 금속유기의 전도체를 사용한 구리의 서로 다른 발란스 상태(valance state)들의 저온에서의 직접 형성을 허용한다. 그러나, 마이크로파 전력, 기판 온도, 및 가스 산화체의 혼합, N2O 또는 O와 같은 공정 파라미터들의 분별있는 선택이 금속의 구리, Cu2O 또는 CuO의 형성을 허용한다는 것에 주목한다.In another technique, a copper oxide film as reported by K.Santra et al. In "Thin Solid Fims", Vol. 213, No. 2, 226-9 (1992), incorporated herein by reference. Are deposited on the substrates by evaporating the copper of the metal via a plasma method in the presence of a constant oxygen pressure. The oxide of the first copper “as much as deposited” is changed to the oxide of the second copper after annealing. In addition, as reported by H. Holzsuch et al. In "Applied Physics A", Vol. A51, No. 6, 486-90 (1990), which are incorporated herein by reference, copper oxide films are formed from precursors ( as a precursor) by CVD using acetylacetone copper. Holzsuch found that an increase in the temperature of the substrate alters the phases of deposition from Cu 2 O + CuO to Cu. At temperatures greater than 500 ° C., the deposition rates were high, but the films were mainly copper of the metal. In addition, as introduced by B. Wisniesky et al. In "Journal de Physique," Vol. 1, No. C2, 389 to 95 (1991), incorporated herein by reference, microwave CVD as an innovative technique is the volatility of acetylacetone copper. Allowing the direct formation at low temperatures of the different balance states of copper using metalorganic conductors. However, it is noted that the sensible selection of microwave power, substrate temperature, and gas oxidant mixing, process parameters such as N 2 O or O allows the formation of copper, Cu 2 O or CuO of the metal.
T.Mruyama가 참조로서 본원에 합체되는 "태양 에너지 물질들 및 태양 전지들(Solar Energy Materials and Solar Cells)", Vol.56, No.1, 85 내지 92(1998)에 최근에 보고한 다른 방법에 따르면, 다결정 구리 산화물 박막들은 대기압력 CVD 방법에 의해 산소 및 구리 디피발로이메탄테(copper dipivaloymethanate)로부터 형성되었다. 더 근래에, Y.Matsuura 등이 참조로서 본원에 합체되는 "응용 광학(Applied Optics)", vol.38, No.9, 1700 내지 3(1999)에 보고한 바와 따르면, 구리 산화물의 유전체막은 CVD 공정에서 전구체로서 금속 아테틸아세톤네이트를 사용함으로써 Ag 코팅된 유리 모세관의 내부에 침착된다. 구리 산화물 침착은 화학과 열에 대해서 매우 큰 내성이 있음이 발견되었다.Other methods recently reported in "Solar Energy Materials and Solar Cells", Vol. 56, No. 1, 85-92 (1998), incorporated by reference by T. Mruyama Polycrystalline copper oxide thin films were formed from oxygen and copper dipivaloymethanate by atmospheric pressure CVD. More recently, as reported by Y. Matsura et al. In "Applied Optics", vol. 38, No. 9, 1700-3 (1999), a dielectric film of copper oxide is known as CVD. It is deposited inside the Ag coated glass capillary by using metal atetylacetonate as precursor in the process. Copper oxide deposition has been found to be very resistant to chemistry and heat.
마지막으로, 구리 산화물을 침착하는 2개의 다른 방법들이 또한 참조로서 본원에 합체된다. 최근에 M.Shurr 등이 "얇은 고체막들(Thin Solid Films)", Vol.342, No.1-2, 266 내지 9(1999)에 보고한 바에 따르면, CuO의 초박막들은 유기의 전구체를 사용하는 랭뮤어 블로젯(L-B; Langmuir-blodgett) 다층막들로부터 형성되고, 여기서 L-B 다층막들은 Cu-아라크히데이트(Cu-arachidate)로 이루어지며, 유기 소자들은 써모 이탈(thermo-desorption) 또는 UV 이탈 중 어느 하나에 의해 제거된다. 구리산화물막들을 성장시키는 다른 기술은 R.Leuchtner 등에 의해 "에피택셜 산화물 박막 Ⅱ(Epitaxial Oxide Thin Films Ⅱ"), Materials Research Society Symposium Proceedings, Vol.401, 551 내지 56(1995)에 보고된다. 여기서, 구리 산화물 막들은 구리 금속 또는 구리 산화물 타켓 중 어느 하나로 펄스 레이저 침착(PLD; pulsed laser deposition)을 사용하여 성장된다.Finally, two other methods of depositing copper oxides are also incorporated herein by reference. Recently reported by M. Shurr et al. In "Thin Solid Films", Vol. 342, No. 1-2, 266 to 9 (1999), ultra thin films of CuO use organic precursors. Is formed from Langmuir-blodgett (LB) multilayers, wherein the LB multilayers are made of Cu-arachidate, and the organic devices are in thermo-desorption or UV escape It is removed by either. Another technique for growing copper oxide films is reported by R. Leuchtner et al. In "Epitaxial Oxide Thin Films II", Materials Research Society Symposium Proceedings, Vol. 401, 551-56 (1995). Here, the copper oxide films are grown using pulsed laser deposition (PLD) with either copper metal or copper oxide targets.
도 2를 참조하면, 구리 산화물의 얇은 층(220)을 상기 개략한 웨이퍼(210) 상에 침착한 후, 금속 라인 패턴(215)은 제 1 포토레지스트층(230)을 이용하여 표준 광학 리소그래픽에 의해 규정된다. 포토레지스트층(230)의 두께는 금속 라인(215)의 두께와 매칭하도록 조심스럽게 선택된다. 도 3을 참조하면, 노출된 구리 산화물(220)은 예를 들어, 본원에 참조로서 합체되는, 동시 계류중이고 공동 양도된 특허출원 "도전 재료 패터닝 방법(CONDUCTIVE MATERIAL PATTERNING METHODS)" 제목의 마이크론 도켓 제99-0671호에 기재된 방법을 포함한, 전통적인 또는 이후 개발된 공정들에 따른 UV 포토 감소에 의해 원 위치에서 구리층(240)으로 변경된다. 구리막(250)은 선택적인 CVD 또는 무전해 도금 중 어느 하나에 의해 소망의 두께로 선택적으로 침착된다. 이들 단계 후, 평면 표면(255)은 CMP 없는 연속하는 단계들을 위해 제공된다.Referring to FIG. 2, after depositing a
도 4에 도시된 바와 같이, 비아 홀(280)이 또한 제조될 수 있다. 구리 산화물의 제 2 시드층(260)은, 상술된 바와 같이, 구리 산화물의 제 1 층(220)을 침착하는 것과 같은 방법으로 제 1 포토레지스트층(230) 및 구리층(250) 상에 침착된다. 그 다음, 비아 홀 리소그래피는 비아(280)의 길이에 대응하는 두께를 갖는 포토레지스트층(270)을 사용하여 실행된다. 도 5를 참조하면, 노출된 구리 산화물(290)은, 상술한 바와 같이, UV 포토 감소에 의해 원 위치에서 구리로 변환된다. 구리막(295)은 선택적인 CVD 또는 무전해 도금 중 어느 하나에 의해 소망의 두께로 선택적으로 침착된다. 다시, 제 2 포토레지스트층(270)의 두께는 비아(280)의 두께와 매치하도록 조심스럽게 선택된다. 전과 같이, 이들 단계 후, 평면 표면(297)이 CMP 없는 연속하는 단계들을 위해 제공된다.As shown in FIG. 4, via
소정의 순서로 전수한 공정을 반복함으로써, 기재된 바와 같이 많은 층들이 다층 상호접속 구조들을 개발하기 이해 제조될 수 있다.By repeating the process handed down in a certain order, many layers can be fabricated to develop multilayer interconnect structures as described.
도 6에 도시되는 대안의 실시예들에서, 전술한 공정은 구리 산화물층(220) 및 제 1 포토레지스트층(230) 사이의 절연층(300)과 조합될 수 있다. 절연층(300)은 SiO2 또는 상기 개요의 제 1 포토 감소 단계 동안 UV 광을 전송하지 않는 등가 재료로 구성될 수 있다.In alternative embodiments shown in FIG. 6, the process described above may be combined with an insulating
고성능 패키지의 응용에 있어서, 전술한 단계들 이후, 사용된 포토레지스트층들(230, 270)은 저유전 상수 절연층으로서 남겨지거나 사용될 수 있다. 또한, 저항이 높고 그리하여 그들 속에 거의 절연하는 구리 산화물의 시드층들(220, 260)은, 10 미크론보다 더 큰 라인 간격이라고 추측되는 라인들 사이의 전류 누설이 신호들보다 현저하게 더 낮을 수 있기 때문에 제자리에 남겨질 수 있다.In the application of a high performance package, after the foregoing steps, the photoresist layers 230 and 270 used may be left or used as a low dielectric constant insulating layer. In addition, the seed layers 220 and 260 of copper oxide, which have high resistance and thus almost insulate therein, may have significantly lower current leakage between the lines, which is assumed to be line spacing greater than 10 microns. It can be left in place.
ULSI 칩들의 응용에 있어서, 사용된 포토레지스트층들은 산소 플라즈마 애싱(oxygen plasa ashing)에 의해 제거되고, 사용된 구리 산화물 시드층들(220, 250)은 상기 Wisiniewsky 등에 기술된 바와 같이 에칭에 의해 제거된다. 이런 방법의 채용은, 동시 계류중이고 공동 양도된 특허출원 "집적 회로들에서 구리 재선을 제조하는 방법 및 장치(METHODS AND APPARATUS FOR MAKING A COPPER WIRING IN INTEGRATED CIRCUITS)" 제목의 미국 특허출원 제09/484,303호에 기재된 재료들 및 방법들로 패시베이션될 수 있는 완성된 에어-브리지 구조(air-bridge structure)를 남기게 되며, 이는 본원에 참조로서 합체된다. 원한다면, 에어 공간은 하나의 작동에서 적당한 유전체층으로 채워질 수 있다.In applications of ULSI chips, the photoresist layers used are removed by oxygen plasma ashing, and the copper oxide seed layers 220 and 250 used are removed by etching as described above in Wisiniewsky et al. do. The adoption of this method is described in US patent application Ser. No. 09 / 484,303 entitled “METHODS AND APPARATUS FOR MAKING A COPPER WIRING IN INTEGRATED CIRCUITS,” which is co-pending and jointly assigned. It leaves a complete air-bridge structure that can be passivated with the materials and methods described in this patent, which is incorporated herein by reference. If desired, the air space can be filled with a suitable dielectric layer in one operation.
상술한 예시적인 방법에서, 지지되지 않는 긴 라인들이 없도록 IC칩들이 설계될 거라고 추측한다. 공정동안 그의 중량으로 인해 훠어질 수 있는 더 긴 라인들을 위해, 미국특허 제5,891,797호에 기술된 절차가 고려되어야 하며, 이는 본원에 참조로서 합체된다. 넓은 라인들이 몇 개의 가까운 최소의 폭과 간격의 라인들로 분해되기 때문에 배선의 상위 레벨들 위의 구리배선 라인들의 폭을 제한하고, 이것은 하위 레벨들 위의 포토레지스트들의 제거를 가능하게 하고, 에어-브리지 구조를 개설하도록 구조에서 충분한 공간들을 확보할 수 있다.In the exemplary method described above, it is assumed that IC chips will be designed so that there are no long lines that are not supported. For longer lines that may break due to its weight during the process, the procedure described in US Pat. No. 5,891,797 should be considered, which is incorporated herein by reference. The wide lines decompose into several near minimum width and spacing lines, thus limiting the width of the copper wiring lines above the upper levels of the wiring, which allows removal of the photoresist above the lower levels, Sufficient space can be secured in the structure to establish a bridge structure.
요약하면, 개시한 것은 구리 산화물 시드층들을 갖는 선택적인 구리의 침착을 이용하여 다층 구리 상호접속들 구조들을 제조하는 신규의 방법이다. CMP의 많은 소모적인 단계들이 제거되고, 단순화되며, 확고한 제조 단계들이 고 성능 패키징 및 USLI 칩들을 위해 도입된다. In summary, what is disclosed is a novel method of fabricating multilayer copper interconnect structures using selective copper deposition with copper oxide seed layers. Many consuming steps of CMP are eliminated, simplified, and robust manufacturing steps are introduced for high performance packaging and USLI chips.
본원에 본 발명의 다양한 실시예들을 자세히 설명하고 기술하였지만, 본 발명의 정신으로부터 벗어나지 않고 그 안에 또한 그에 수정 및 부가할 수 있으며, 이는 본 발명의 정신과 첨부된 청구항의 범위내에 포함되는 것이 자명하다.
While various embodiments of the present invention have been described and described in detail herein, modifications and additions thereto may be made without departing from the spirit of the invention, which are obviously intended to be included within the spirit of the invention and the scope of the appended claims.
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