KR960015731A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR960015731A
KR960015731A KR1019940026836A KR19940026836A KR960015731A KR 960015731 A KR960015731 A KR 960015731A KR 1019940026836 A KR1019940026836 A KR 1019940026836A KR 19940026836 A KR19940026836 A KR 19940026836A KR 960015731 A KR960015731 A KR 960015731A
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KR
South Korea
Prior art keywords
forming
layer
less
barrier layer
insulating film
Prior art date
Application number
KR1019940026836A
Other languages
Korean (ko)
Other versions
KR0141932B1 (en
Inventor
라관구
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940026836A priority Critical patent/KR0141932B1/en
Publication of KR960015731A publication Critical patent/KR960015731A/en
Application granted granted Critical
Publication of KR0141932B1 publication Critical patent/KR0141932B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 반도체기판 위에 산화막을 형성하는 공정과, 상기 산화막위에 구리를 증착시켜 금속층을 형성하는 공정과, 상기 금속층을 사진식각법으로 패터닝한 후 결과물 전면에 HMDS와 같은 유기실란을 도포하여 장벽층을 형성하는 공정과, 상기 장벽층 위에 SOG를 도포하여 절연막을 형성하는 공정과, 상기 절연막 위에 표면안정화층을 형성하는 공정을 포함하여 구성되며, 상기 장벽층과 절연막이 구리가 다른막으로 침투하는 것을 방지하여 0.3㎛이하의 미세패턴 배선의 제작을 용이하게 하며, 사진식각공정을 종래보다 감소시켜 제조가를 감소 및 양품률을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an oxide film on a semiconductor substrate; depositing copper on the oxide film to form a metal layer; and patterning the metal layer by photolithography and then HMDS on the entire surface of the resultant product. Forming a barrier layer by applying an organic silane, a process of forming an insulating film by applying SOG on the barrier layer, and forming a surface stabilization layer on the insulating film. The insulating film prevents copper from penetrating into another film, thereby facilitating the fabrication of fine pattern wirings of 0.3 μm or less, and reducing the photolithography process compared to the prior art, thereby reducing manufacturing costs and improving yield.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 반도체장치의 제조방법을 도시한 단면도.2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.

Claims (7)

반도체기판 위에 산화막을 형성하는 공정과, 상기 산화막 위에 구리를 증착시켜 금속층을 형성하는 공정과, 상기 금속층을 사진식각법으로 패터닝한 후 결과물 전면에 유기실란을 도포하여 장벽층을 형성하는 공정과, 상기 장벽층 위에 절연물질을 도포하여 절연막을 형성하는 공정과, 상기 절연막 위에 표면안정화층을 형성하는 공정을 포함하여 구성된 것을 특징으로 하는반도체장치의 제조방법.Forming an oxide film on a semiconductor substrate, depositing copper on the oxide film to form a metal layer, patterning the metal layer by photolithography, and then applying an organic silane to the entire surface of the resultant to form a barrier layer; And forming a surface insulating layer by applying an insulating material on the barrier layer, and forming a surface stabilization layer on the insulating layer. 제1항에 있어서, 상기 유기실란은 HMDS임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the organosilane is HMDS. 제1항에 있어서, 상기 장벽층은 두께가 1㎛ 이하임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the barrier layer has a thickness of 1 μm or less. 제1항에 있어서, 상기 절연막은 P가 20wt% 이하 도핑된 SOG 임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the insulating layer is SOG doped with P of 20 wt% or less. 제1항에 있어서, 상기 절연막은 두께가 2㎛ 이하임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the insulating layer has a thickness of 2 μm or less. 제2항에 있어서, 상기 HMDS는 500℃이하의 열처리공정을 거쳐 형성됨을 특징으로 하는 반도체장치의 제조방법.The method of claim 2, wherein the HMDS is formed through a heat treatment of 500 ° C. or less. 제4항에 있어서, 상기 SOG는 500℃ 이하의 열처리공정을 거쳐 형성됨을 특징으로 하는 반도체장치의 제조방법.The method of claim 4, wherein the SOG is formed by a heat treatment of 500 ° C. or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026836A 1994-10-20 1994-10-20 Method of manufacture in semiconductor device KR0141932B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940026836A KR0141932B1 (en) 1994-10-20 1994-10-20 Method of manufacture in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940026836A KR0141932B1 (en) 1994-10-20 1994-10-20 Method of manufacture in semiconductor device

Publications (2)

Publication Number Publication Date
KR960015731A true KR960015731A (en) 1996-05-22
KR0141932B1 KR0141932B1 (en) 1998-07-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940026836A KR0141932B1 (en) 1994-10-20 1994-10-20 Method of manufacture in semiconductor device

Country Status (1)

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KR (1) KR0141932B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459332B1 (en) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459332B1 (en) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device

Also Published As

Publication number Publication date
KR0141932B1 (en) 1998-07-15

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