KR970054472A

KR970054472A - Thin film transistor and its manufacturing method

Info

Publication number: KR970054472A
Application number: KR1019950065933A
Authority: KR
Inventors: 최준후; 정창오
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-29
Filing date: 1995-12-29
Publication date: 1997-07-31

Abstract

본 발명은 박막 트랜지스터의 게이트 전극 구조에 관한 것으로 양극 산화공정을 생략하여 마스크의 수를 줄이고 후속공정에서 발생하는 게이트의 침식을 억제하는데 목적이 있다.The present invention relates to a structure of a gate electrode of a thin film transistor, and aims to reduce the number of masks by suppressing the anodic oxidation process and to suppress erosion of the gate generated in a subsequent process.

이를 위한 본 발명은 게이트전극, 게이트 절연막, 화소전극, 비정질 실리콘막, n+Si 오믹층이 순차적으로 적층 형성되고, 그 위에 드레인전극과 소오스 전극이 형성되며 전면에 SiN 보호막이 도포되어 형성된 박막 트랜지스터에있어서, 상기 게이트전극은 Al-Nd로 이루어진 하부전극과 Al로 이루어진 상부전극의 이중 구조로 구성된 것을 특징으로 한다.According to the present invention, a thin film transistor formed by sequentially stacking a gate electrode, a gate insulating film, a pixel electrode, an amorphous silicon film, and an n + Si ohmic layer, a drain electrode and a source electrode formed thereon, and a SiN protective film coated on the entire surface thereof. In the above, the gate electrode is characterized in that the dual structure of the lower electrode made of Al-Nd and the upper electrode made of Al.

상기와 같은 구조의 본 발명의 박막 트랜지스터는 Al을 게이트로 사용할 때에 행해야 하는 양극산화 공정을 생략할 수 있어 별도의 마스크를 필요로 하지 않아 제조공정을 단순화할 수 있다. 또한 Al-Nd와 Al 각각의 두께를 적당히 조합함으로써 후속공정의 변동에 대해서 박막 내부의 열스트레스 조절이 가능하므로 쉽게 대응 할 수 있다.The thin film transistor of the present invention having the above structure can omit the anodization process to be performed when Al is used as a gate, and thus a manufacturing process can be simplified without requiring a separate mask. In addition, by appropriately combining the thickness of each of Al-Nd and Al, it is possible to easily cope with the heat stress control in the thin film against the variation of the subsequent process.

Description

Thin film transistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 박막 트랜지스터의 구조.2 is a structure of a thin film transistor of the present invention.

Claims

The gate electrode 2, the gate insulating film 3, the pixel electrode 4, the amorphous silicon film 5, and the n + Si ohmic layer 6 are sequentially stacked on the drain electrode 7 and the source electrode. (8) is formed and a thin film transistor formed by coating a SiN protective film (7) on the entire surface, wherein the gate electrode (2) is a double of the lower electrode (2a) made of Al-Nd and the upper electrode (2b) made of Al. A thin film transistor comprising a structure.

The thin film transistor according to claim 1, wherein the thickness of the lower electrode (2a) is set to 150 nm and the thickness of the upper electrode (2b) is set to 50 nm.

The gate electrode 2 is formed, and the gate insulating film 3, the pixel electrode 4, the amorphous silicon film 5, and the n + Si ohmic layer 6 are sequentially stacked, followed by the drain electrode 7 and the source. In the method of manufacturing a thin film transistor in which a SiN protective film 7 is coated on the entire surface after the electrode 8 is formed, the gate electrode 2 is formed by sequentially stacking and patterning Al-Nd and Al, and then exposing and etching. Thin film transistor manufacturing method characterized in that.

※ Note: The disclosure is based on the initial application.