KR970023706A - Method for manufacturing gate electrode using aluminum-hafnium alloy to form terminal solid solution - Google Patents

Method for manufacturing gate electrode using aluminum-hafnium alloy to form terminal solid solution Download PDF

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KR970023706A
KR970023706A KR1019950034297A KR19950034297A KR970023706A KR 970023706 A KR970023706 A KR 970023706A KR 1019950034297 A KR1019950034297 A KR 1019950034297A KR 19950034297 A KR19950034297 A KR 19950034297A KR 970023706 A KR970023706 A KR 970023706A
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South Korea
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gate electrode
thin film
film transistor
manufacturing
aluminum
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KR1019950034297A
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Korean (ko)
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KR0169379B1 (en
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송진호
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Abstract

박막 트랜지스터의 게이트 전극에 터미날 고상용액을 형성하는 알루미늄-하프늄 합금계를 사용하여 침전강화를 적용하고 어닐링 공정을 추가하여 2차상으로서 단일 성분으로 되어 있는 화합물만을 석출시킴으로써 식각 전기의 발생을 억제하고 기계적 강화를 극대화시켜 양극산화막만으로는 해결할 수 없었던 힐록과 크랙 등의 기계적 성질에 관한 여러가지 문제들을 개선하고자 하는데에 본 발명의 목적이 있다.Precipitation strengthening is applied by using an aluminum-hafnium alloy system that forms a terminal solid solution on the gate electrode of the thin film transistor, and an annealing process is added to precipitate only the compound having a single component as a secondary phase to suppress the generation of etching electricity and The object of the present invention is to improve various problems related to mechanical properties such as hillock and cracks that could not be solved by maximizing the strengthening alone.

Description

터미날 고상용액을 형성하는 알루미늄-하프늄 합금을 이용한 게이트 전극의 제조방법Method for manufacturing gate electrode using aluminum-hafnium alloy to form terminal solid solution

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 의한 탑-산화인듐틴(Top-ITO)구조를 지닌 박막 트랜지스터 기판의 단면도.2 is a cross-sectional view of a thin film transistor substrate having a top indium tin oxide (Top-ITO) structure according to an embodiment of the present invention.

Claims (14)

세정한 투명 유리 기판위에 알루미늄과 그외에 첨가원소를 포함하는 알루미늄 합금을 증착하는 공정, 자외선에 의해 감광하는 레지스트를 도포하고 레지스트를 프리베이크해서 경화시키는 공정, 자외선에 의해 노광, 현상하는 공정 포스트베이크한 뒤 식각하여 패터닝하지 않은 부분을 제거하는 공정, 양극산화 공정 그리고 활성 증착공정을 포함하는 박막 트랜지스터용 게이트 전극 제조방법에 있어서, 식각 공정후에 어닐링 공정을 더욱 포함하는 것을 특징으로 하는 박막 트랜지스터용 게이트 전극의 제조방법.A process of depositing an aluminum alloy containing aluminum and other elements on the cleaned transparent glass substrate, a process of applying a resist that is exposed to ultraviolet rays, prebaking the resist to cure it, and a process of exposing and developing with ultraviolet rays post-baking A method of manufacturing a gate electrode for a thin film transistor comprising a step of removing an unpatterned portion by etching and then anodizing and an active deposition process, the gate electrode of a thin film transistor further comprising an annealing process after the etching process. Method of manufacturing the electrode. 제1항에 있어서, 상기한 알루미늄 함금은 알루미늄-하프늄 또는 알루미늄-게르마늄인 이중 알루미늄 합금인 박막 트랜지스터용 게이트 전극의 제조방법.The method of claim 1, wherein the aluminum alloy is a double aluminum alloy of aluminum hafnium or aluminum germanium. 제1항에 있어서, 상기한 첨가원소는 터미날 고상용액을 형성하는 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 1, wherein the additive element forms a terminal solid solution. 제1항 또는 제3항에 있어서, 상기한 첨가원소의 첨가량은 최대 터미날 용해도 근처에서 0.5%∼2%의 범위안에 있는 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 1 or 3, wherein the amount of the additive element added is in the range of 0.5% to 2% near the maximum terminal solubility. 제1항에 있어서, 상기 어닐링 공정은 열역학적으로 안정한 단일조성의 화합물을 석출하는 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of claim 1, wherein the annealing process precipitates a thermodynamically stable single compound. 제1항 또는 제5항에 있어서, 상기 어닐링 공정은 공정 후에 석출되는 2차상의 조성이 HfAl3인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 1 or 5, wherein the annealing step has a composition of HfAl 3 as a secondary phase deposited after the step. 제1항 또는 제5항에 있어서, 상기 어닐링 공정은 공정의 온도가 300∼400℃의 범위인 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 1 or 5, wherein the annealing step has a temperature in the range of 300 to 400 ° C. 세정한 투명 유리 기판위에 알루미늄 합금을 증착, 포토, 식각, 양극산화, 활성증착하여 게이트 전극을 형성하는 공정, 상기 게이트 전극 위에 게이트 절연막을 형성하는 공정, 상기 절연막 위에 활성비정질 실리콘층을 형성하는 공정, 상기 절연막 위에 박막 트랜지스터가 되는 부분만을 패터닝해서 비정질의 옴접촉층을 형성하는 공정, 상기 비정질의 옴접촉층 위에 소스 전극과 드레인 전극을 형성하는 공정 그리고 보호막을 형성하는 공정, 상기 절연막 위의 화소전극이 되는 부분을 산화인듐틴의 금속산화막으로 화소전극을 형성하는 공정을 포함하는 박막 트랜지스터기판의 제조방법에 있어서, 상기 게이트 전극을 형성하는 공정은 식각후에 어닐링 공정을 더욱 포함하는 것을 특징으로 하는 박막 트랜지스터 기판의 제조방법.Depositing an aluminum alloy on the cleaned transparent glass substrate, forming a gate electrode by photo, etching, anodizing, and active depositing, forming a gate insulating film on the gate electrode, and forming an active amorphous silicon layer on the insulating film Forming a amorphous ohmic contact layer by patterning only a portion of the thin film transistor on the insulating film, forming a source electrode and a drain electrode on the amorphous ohmic contact layer, and forming a protective film; a pixel on the insulating film A method of manufacturing a thin film transistor substrate comprising forming a pixel electrode using a metal oxide film of indium tin oxide as a part of the electrode, wherein the forming of the gate electrode further includes an annealing process after etching. Method of manufacturing a thin film transistor substrate. 제8항에 있어서, 상기한 알루미늄 합금은 알루미늄-하프늄 또는 알루미늄-게르마늄인 이중 알루미늄 합금인 박막 트랜지스터용 게이트 전극의 제조방법.The method of claim 8, wherein the aluminum alloy is a double aluminum alloy of aluminum hafnium or aluminum germanium. 제8항에 있어서, 상기한 첨가원소는 터미날 고상용액을 형성하는 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 8, wherein the additive element forms a terminal solid solution. 제8항 또는 제10항에 있어서, 상기한 첨가원소의 첨가량은 최대 터미날 용해도 근처에서 0.5%∼2%의 범위에 있는 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 8 or 10, wherein the addition amount of the additional element is in the range of 0.5% to 2% near the maximum terminal solubility. 제8항에 있어서, 상기 어닐링 공정은 열역학적으로 안정한 단일조성의 화합물을 석출하는 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of claim 8, wherein the annealing process precipitates a thermodynamically stable single compound. 제8항 또는 제12항에 있어서, 상기 아닐린 공정은 공정 후에 석출되는 2차상의 조성이 HfAl3인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 8 or 12, wherein in the aniline step, the composition of the secondary phase precipitated after the step is HfAl 3 . 제8항 또는 제12항에 있어서, 상기 어닐링 공정은 공정의 온도가 300∼400℃의 범위인 것인 박막 트랜지스터용 게이트 전극의 제조방법.The method of manufacturing a gate electrode for a thin film transistor according to claim 8 or 12, wherein the annealing step has a temperature in a step of 300 to 400 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034297A 1995-10-06 1995-10-06 Gate electrode manufacturing method for al-hf alloy KR0169379B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100694482B1 (en) * 2001-07-18 2007-03-12 닛코킨조쿠 가부시키가이샤 Hafnium silicide target for forming gate oxide film, and manufacturing method thereof
KR100720082B1 (en) * 1998-03-13 2007-11-12 삼성전자주식회사 Manufacturing method of liquid crystal display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100720082B1 (en) * 1998-03-13 2007-11-12 삼성전자주식회사 Manufacturing method of liquid crystal display device
KR100694482B1 (en) * 2001-07-18 2007-03-12 닛코킨조쿠 가부시키가이샤 Hafnium silicide target for forming gate oxide film, and manufacturing method thereof

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