KR930018756A - Thin film transistor of liquid crystal display and manufacturing method - Google Patents

Thin film transistor of liquid crystal display and manufacturing method Download PDF

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Publication number
KR930018756A
KR930018756A KR1019920002971A KR920002971A KR930018756A KR 930018756 A KR930018756 A KR 930018756A KR 1019920002971 A KR1019920002971 A KR 1019920002971A KR 920002971 A KR920002971 A KR 920002971A KR 930018756 A KR930018756 A KR 930018756A
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South Korea
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semiconductor layer
thin film
film transistor
photoresist pattern
high concentration
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KR1019920002971A
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Korean (ko)
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KR950003942B1 (en
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김남덕
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김광호
삼성전자 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors

Abstract

LCD TFT의 소오스전극 및 드레인전극을 게이트 절연막과 반도체층의 사이에 리프트 오프방법으로 형성하였다. 따라서 소오스전극과 드레인전극 사이의 직렬저항이 감소하여 신호전달속도를 증가시킬 수 있다. 또한, 반도체층의 두께를 얇게 형성하여 TFT의 오프전류를 감소시킬 수 있어 LCD의 신뢰성 및 효율을 향상시킬 수있다. 또한, 채널영역 형성시 반도체층의 표며에 전위등의 결함발생을 방지하여 TFT의 전기적 특성을 향상시킬 수 있다.The source electrode and the drain electrode of the LCD TFT were formed by the lift-off method between the gate insulating film and the semiconductor layer. Therefore, the series resistance between the source electrode and the drain electrode can be reduced to increase the signal transfer speed. In addition, the thickness of the semiconductor layer can be reduced to reduce the off current of the TFT, thereby improving the reliability and efficiency of the LCD. In addition, when the channel region is formed, defects such as dislocations are prevented from occurring on the surface of the semiconductor layer, thereby improving the electrical characteristics of the TFT.

Description

액정표시장치의 박막트랜지스터 및 그 제조방법Thin film transistor of liquid crystal display and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3(a)~(d)도는 이 발명의 일실시예에 따른 액정표시장치의 박막트랜지스터의 제조공정도이다.3 (a) to 3d are manufacturing process diagrams of the thin film transistor of the liquid crystal display according to the exemplary embodiment of the present invention.

Claims (12)

유리재질의 절연기판과, 상기 절연기판상에 형성되어 있는 게이트전극과, 상기 구조의 전표면에 형성되어 있는 게이트 절연막과, 상기 게이트 절연막의 표면에 상기 게이트전극을 사이에 두고 소정간격 이격되어 게이트 절연막이 노출되도록 형성된 고농도 반도체층과, 상기 고농도 반도체층의 상부표면에 형성된 소오스전극 및 드레인전극과, 상기 소오스전극 및 드레인전극에 의해 노출된 게이트 절연막의 상부에 상기 소오스 전극 및 드레인전극과 소정부분 겹치도록 형성된 반체도층과, 상기 반도체층의 상부에 형성되어 있는 보호층을 구비하는 액정표시장치의 박막트랜지스터.A glass insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the entire surface of the structure, and a gate spaced apart by a predetermined interval between the gate insulating films A high concentration semiconductor layer formed to expose the insulating layer, a source electrode and a drain electrode formed on an upper surface of the high concentration semiconductor layer, and a source portion and a drain electrode and a predetermined portion on the gate insulating layer exposed by the source electrode and the drain electrode. A thin film transistor of a liquid crystal display device comprising a semiconducting layer formed so as to overlap and a protective layer formed on the semiconductor layer. 제1항에 있어서, 상기 게이트전극이 Ti, Al, Cr, Ta 및 W등으로 이루어지는 군중에서 임의로 선택되는 하나의 금속으로 형성되는 액정표시장치의 박막트랜지스터.The thin film transistor of claim 1, wherein the gate electrode is formed of one metal arbitrarily selected from a crowd consisting of Ti, Al, Cr, Ta, and W. 제1항에 있어서, 상기 게이트 절연막이 산화규소 및 질화규소로 이루어지는 군에서 임의로 선택되는 하나의 절연물질로 형성되는 액정표시장치의 박막트랜지스터.The thin film transistor of claim 1, wherein the gate insulating layer is formed of one insulating material arbitrarily selected from the group consisting of silicon oxide and silicon nitride. 제1항에 있어서, 상기 고농도 반도체층이 n형 불순물이 고농도로 도핑된 다결정규소, 비정질규소 및 수소화된 비정질규소로 이루어지는 군에서 임의로 선택되는 하나의 반도체로 형성되는 액정표시장치의 박막트랜지스터.The thin film transistor of claim 1, wherein the high concentration semiconductor layer is formed of one semiconductor arbitrarily selected from the group consisting of polycrystalline silicon, amorphous silicon, and hydrogenated amorphous silicon doped with high concentration of n-type impurities. 제1항에 있어서, 상기 소오스전극 및 드레인전극이 Al,Cr,Ta 및 W등으로 이루어지는 군에서 임의로 선택되는 하나의 금속으로 형성되는 액정표시장치의 박막트랜지스터.2. The thin film transistor of claim 1, wherein the source electrode and the drain electrode are formed of one metal arbitrarily selected from the group consisting of Al, Cr, Ta, and W. 제1항에 있어서, 상기 소오스전극 및 드레인전극이 금속 규화물로 형성되는 액정표시장치의 박막트랜지스터.The thin film transistor of claim 1, wherein the source electrode and the drain electrode are formed of metal silicide. 제1항에 있어서, 상기 반도체층이 다결정규소, 비정질규소 및 수소화된 비정질규소로 이루어지는 군에서 임의로 선택되는 하나의 반도체로 형성되는 액정표시장치의 박막트랜지스터.The thin film transistor of claim 1, wherein the semiconductor layer is formed of one semiconductor arbitrarily selected from the group consisting of polycrystalline silicon, amorphous silicon, and hydrogenated amorphous silicon. 제1항에 있어서, 상기 보호층이 산화규소, 질화규소로 이루어지는 군에서 선택되는 임의의 절연물질로 형성되는 액정표시장치의 박막트랜지스터.The thin film transistor of claim 1, wherein the protective layer is formed of any insulating material selected from the group consisting of silicon oxide and silicon nitride. 유리재질의 절연기판상에 통상의 방법으로 게이트전극을 형성하는 공정과, 상기 구조의 전표면에 게이트 절연막을 형성하는 공정과, 상기 게이트전극상의 게이트 절연막의 표면에 보호되도록 제1감광막 패턴을 형성하는 공정과, 상기 구조의 전표면에 고농도 반도체층을 형성하는 공정과, 상기 고농도 반도체층의 상부에 도전층을 형성하는 공정과, 상기 제1감광막 패턴과 제1감광막 패턴상의 고농도 반도체층 및 도전층을 순차적으로 제거하여 게이트 절연막을 노출시켜 소오스전극 및 드레인전극을 형성하는 공정과, 상기 구조의 전표면에 반도체층을 형성하는 공정과, 상기 반도체층의 상부에 보호층을 형성하는 공정과, 상기 고농도 반도체층에 의해 노출된 게이트 절연막과 상기 게이트 절연막에 인접한 소오스전극 및 드레인전극의 일부가 보호되도록 상기 보호층의 상부에 제2감광막 패턴을 형성하는 공정과, 상기 제2감광막 패턴에 의해 노출된 상기 보호층 및 반도체층을 순차적으로 제거한 후 상기 제2감광막 패턴을 제거하는 공정을 포함하여 이루어지는 액정표시장치의 박막트랜지스터 제조방법.Forming a gate electrode on a glass insulating substrate in a conventional manner; forming a gate insulating film on the entire surface of the structure; and forming a first photoresist pattern to protect the surface of the gate insulating film on the gate electrode. A step of forming a high concentration semiconductor layer on the entire surface of the structure, a step of forming a conductive layer on top of the high concentration semiconductor layer, a high concentration semiconductor layer on the first photoresist pattern and the first photoresist pattern, and conductive Removing the layers sequentially to expose the gate insulating film to form a source electrode and a drain electrode, forming a semiconductor layer on the entire surface of the structure, forming a protective layer on top of the semiconductor layer; A portion of the gate insulating film exposed by the high concentration semiconductor layer and the source electrode and the drain electrode adjacent to the gate insulating film are protected. Forming a second photoresist pattern on the upper portion of the protective layer, and sequentially removing the protective layer and the semiconductor layer exposed by the second photoresist pattern, and then removing the second photoresist pattern. Method of manufacturing thin film transistor of liquid crystal display device. 제9항에 있어서, 상기 제1감광막 패턴 형성 공정시게이트전극을 노광마스크로하여 절연기판의 뒷면에서 빛을 조사하는 액정표시장치의 박막트랜지스터의 제조방법.The method of claim 9, wherein the light is irradiated from the rear surface of the insulating substrate using the gate electrode as the exposure mask during the first photoresist pattern forming process. 제9항에 있어서, 상기 제1감광막 패턴을 감광도가 서로 다른 감광물질로 2층으로 적층하여 형성하는 액정표시장치의 박막트랜지스터 제조방법10. The method of claim 9, wherein the first photoresist pattern is formed by stacking the first photoresist pattern in two layers with photosensitive materials having different photosensitivity. 제9항에 있어서, 상기 제1감광막 패턴과 제1감광막 패턴상의 고농도 반도체층 및 도전층을 제거하는 공정을 통상의 리프트 오프공정으로 행하는 액정표시장치의 박막트랜지스터 제조방법.10. The method of manufacturing a thin film transistor of a liquid crystal display device according to claim 9, wherein the step of removing the high concentration semiconductor layer and the conductive layer on the first photoresist pattern and the first photoresist pattern is performed by a normal lift-off process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920002971A 1992-02-26 1992-02-26 Method of manufacturing thin film transistor for lcd KR950003942B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101013625B1 (en) * 2003-12-23 2011-02-10 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101013625B1 (en) * 2003-12-23 2011-02-10 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating the same

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KR950003942B1 (en) 1995-04-21

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