JPH07245406A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor which has a high driving capacity and can operate quickly even if a channel length is reduced. CONSTITUTION:A gate metal 2 is formed on a glass substrate 1. A sate insulation film 3 is formed on the glass substrate 1 and the gate metal 2 and an amorphous silicon layer 4 which becomes a channel region is formed at a position corresponding to the gate metal 2 on it, and ion-implanted amorphous silicon layer 7 which becomes source/drain regions is formed at both sides. A silicon layer 5 containing a crystal which becomes a channel region is formed on the amorphous silicon layer 4 and a silicon layer 8 containing an ion- implanted crystal which becomes source/drain regions is formed at both sides. A channel protection film 6 is formed on the silicon layer 5 containing the crystal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor for driving a liquid crystal or the like.

[0002]

2. Description of the Related Art In a liquid crystal display, an active matrix type LCD using a thin film transistor (TFT) that has a small crosstalk and a large contrast ratio of 100 or more and can obtain an image quality comparable to that of a CRT in displaying a moving image is provided. Is expected. In the future, it is necessary to improve the image quality, increase the number of pixels, and increase the screen size.

For that purpose, it is effective to improve the performance of the TFT, and it is expected that the self-alignment type TFT can make a great improvement especially. The feature of the self-aligned TFT is that a large screen can be formed uniformly even if the accuracy of mask alignment is low, and the capacitance between the electrodes can be reduced by reducing the overlap of the gate, source and drain. is there. In addition, as the channel length can be shortened, the on-current of the TFT can be increased.

FIG. 5 is a sectional view showing the structure of a self-aligned TFT disclosed in Japanese Patent Laid-Open No. 1-183854. As shown in FIG. 5, the gate metal 2 is formed on the glass substrate 1, and the gate insulating film 3 is laminated thereon. Further, an amorphous silicon (a-Si) layer 4 serving as a channel region is formed on the gate electrode 2 at a position corresponding to the gate electrode 2.
And n ⁺ a-Si layers 7 to be source and drain regions are provided on both sides adjacent to the a-Si layer 4, respectively. A silicide layer 9 obtained by reacting metal and silicon is formed on the n ⁺ a-Si layer 7, and a source and drain electrode 10 is provided thereon. A channel protective film 6 is formed on the a-Si layer 4.

When the channel length L shown in FIG. 5 is shortened in order to increase the on-current in the TFT as described above, if the carrier mobility in the channel is constant, the channel length L
It is considered that the on-current increases in inverse proportion to. However, it was confirmed that the on-current was actually smaller than the expected value. This is a phenomenon in which the mobility of the semiconductor forming the channel appears to have decreased. When this mobility is lowered, the driving ability of the TFT is reduced and the TFT cannot operate at high speed.

The present inventors analyzed the cause of the above phenomenon and found that the source and drain regions of the TFT were n ⁺ a-Si.
It was found that the on-current is small due to the existence of the parasitic resistance in the layer 7. It was also found that among the parasitic resistances, the contact resistance between the n ⁺ a-Si layer 7 and the silicide layer 9 in the source and drain regions was particularly high.

[0007]

As described above, in the conventional TFT, there is a problem that the parasitic resistance generated in the source and drain regions is high, so that the driving ability of the TFT is reduced and the TFT cannot operate at high speed. . Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a thin film transistor which has a high driving ability even when the channel length is shortened and operates at high speed.

[0008]

In order to solve the above-mentioned problems, the present invention provides a gate electrode, a channel region provided in contact with the gate electrode, and a channel region provided in contact with the channel region. -In a thin film transistor comprising a source region and a drain region and two wiring electrodes provided in contact with the source region and the drain region, the channel region, the source region and the drain region are amorphous semiconductors. And a surface portion of the source region and the drain region which is connected to the wiring electrode is made of a semiconductor containing crystals.

Silicon or the like is used as the semiconductor. As silicon containing crystals, microcrystalline silicon (μ
Although it is preferable to use c-Si), polycrystalline silicon that is mostly crystallized may be used.

[0010]

According to the present invention, the surface of the source and drain regions in contact with the silicide is silicon containing crystals, and the conductivity is significantly increased as compared with the conventional TFT using only amorphous silicon, resulting in carrier activation. As a result, the contact resistance can be reduced. As a result, it is possible to prevent the on-current from decreasing, and the mobility does not decrease.

[0011]

EXAMPLES The details of the present invention will be described below with reference to examples. (Embodiment 1) FIG. 1 is a sectional view showing the structure of a TFT according to this embodiment, and FIG. 2 is a top view thereof. FIG. 1 is a cross-sectional view of a plane cut in the direction of broken line AA ′ in FIG.

FIG. 3 is a sectional view showing the manufacturing process. 1 to 3, the same numbers are given to the same parts,
The description will be centered on FIG. First, as shown in FIG. 3A, a gate metal 2 made of a MoTa alloy is formed on a glass substrate 1 by a magnetron sputtering method or the like. Examples of the material used for the gate metal include Al and M
Metals such as o, W, and Ti, those obtained by stacking these, or alloys thereof can also be used. Also Al
It is also possible to use the one in which a pattern such as MoTa is formed so as to cover the same by patterning the above. Further, an undercoat film made of an insulating film such as silicon oxide may be formed on the glass substrate 1.

Next, a gate insulating film 3 having a thickness of 350 nm of silicon oxide and a thickness of 50 nm of silicon nitride, an a-Si film 4 having a thickness of 50 nm, and a microcrystalline silicon (μc-Si) film having a thickness of 10 nm. 5. Made of silicon nitride 400nm
The channel protection film 6 having a thickness of 1 is formed by the CVD method. Here, the thickness of the μc-Si film 5 can be changed in the range of about 5 to 20 nm, and the thickness of the channel protective film 6 can be changed in the range of about 200 to 500 nm. Further, the CVD condition for forming the a-Si film 4 is silane: hydrogen = 20: 8.
0, RF power density was 0.03 W / cm ² , and μc−
The conditions for forming the Si film 5 are silane: hydrogen = 5: 9.
5, RF power density is 0.1 W / cm ² . Note that μc
The condition for forming the —Si film 5 is that the ratio of hydrogen is higher than that of the above condition and the RF power density is high.

As a method for forming the μc-Si film 5, a mercury-sensitized photo-CVD method can be used. In that case, silane: hydrogen = 20: 80 can be formed. In this case, 100% silane is sufficient for forming the a-Si film 4.

Next, a positive photoresist is applied, and the back surface of the substrate is irradiated with ultraviolet light to be exposed and developed to form a resist pattern 30 having substantially the same width as the gate electrode 2.
Since the end portion of the channel protective film 6 in the direction shown by the broken line BB ′ in FIG. 2 can be determined by ordinary mask exposure before development here, this step is included in this embodiment. The pattern of the channel protection film 6 may be formed only by mask exposure without using backside exposure. In this case
It is necessary to take an alignment margin based on the mask alignment accuracy with the metal plate 2, but depending on the application it may be practical.

After that, as shown in FIG. 3B, after the channel protection film 6 is etched, impurity atoms are doped into the silicon film. In the case of manufacturing an n-channel TFT, phosphorus may be used as an impurity atom, but in this embodiment, 5% phosphine PH ₃ gas diluted with hydrogen gas is discharged and decomposed to generate ions such as PH _X ⁺ to form a channel. The protective film 6 was used as a mask to accelerate and inject toward the substrate. Accelerating voltage is 30 keV and ion dose is 2 × 10 ¹⁶ / cm ^2.
And Then, annealing for activation was performed at 230 ° C. As a result, n ⁺ becomes the source and drain regions.
A layer of a-Si film 7 and a μc-Si film 8 are formed. The a-Si film 4 and the μc-Si film 5 under the channel protection film 6
Is the channel region.

The ion implantation conditions are phosphine PH.
₃ can be changed within a range of 1 to 20%, an acceleration voltage of 20 to 40 keV, and an ion dose amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ² . The annealing temperature can be changed within the range of 200 to 300 ° C.

The doping method is not limited to the method shown here, and ordinary ion implantation for mass spectrometry may be used, or simple mass separation for removing only hydrogen ions may be performed. A method in which activation is promoted at a temperature of 200 to 300 ° C., or a method of irradiating a laser to diffusely dope the silicon surface from an impurity source can also be used.

Further, as shown in FIG. 3 (c), after cleaning the surface of the silicon for silicidation, Mo is removed.
31 is formed by sputtering, and the silicide layer 9 is formed by patterning to form a semiconductor in an island shape.

Although Mo is used in this embodiment, other metals,
For example, Cr, W, Ti, Pd, Ni, Co or the like or an alloy thereof may be used. Further, it may be annealed at 200 to 300 ° C. after the film formation.

In patterning, the resist pattern for determining the island shape is formed to be narrower than the width of the channel protective film 6 shown in the direction of broken line BB 'in FIG. 2, so that the selectivity between the channel protective film and the silicon film is improved. It is formed by using reactive ion etching (RIE) using a gas containing, for example, chlorine gas. It is also possible to simultaneously etch the channel protective film 6 during etching.

Finally, as shown in FIG. 3D, after Mo used for forming the silicide is removed, a Mo / Al laminated solution is respectively connected to the silicide layer 9 forming the source and drain regions. -, The drain electrode 10 is formed. In this way, the TFT is completed.

Any material other than Mo / Al may be used as the electrode as long as it has conductivity. In this embodiment, n
⁺ The contact resistance between the μc-Si layer 8 and the silicide layer 9 was 10 ^-2 to 10 ^-4 Ωcm ^2, which was improved by 1 to 3 orders of magnitude over the contact resistance of the conventional TFT using only a-Si.

As a result, channel width W / channel length L = 2
Mobility of 0.8 cm ² / Vs with 0 μm / 5 μm TFT
Became. This is almost the same mobility as a TFT having a channel length L = 12 μm. As a result, TFTs with the same channel length
It will operate about 1.6 times faster than.

When the leak current was measured, it was 10 ^−12.
The value was as small as A or less. This is a conventional TFT
The current is about 10 ^-11 A, which is improved by one digit or more.

The reason for this is that since the silicon layer 5 containing crystals is formed on the side of the channel region opposite to the gate electrode 2, the leak current increases even if charges are induced on the channel protective film 6. It is thought that it is because it does not. Conventional TF
In T, when charges are induced on the channel protection film 6,
Since the state of the interface between the channel protective film and the a-Si layer is good, charges flowed through the channel protective film to the a-Si layer, increasing the leak current. (Embodiment 2) FIG. 4 shows a sectional view of a TFT according to this embodiment. Regarding the numbers in the figure, the same parts as in Example 1 are given the same numbers. In this embodiment, the shapes of the source and drain electrodes are different from those in the first embodiment.

Since the manufacturing process is almost the same as that of the first embodiment, only parts different from the first embodiment will be described. After the step of FIG. 3B, the semiconductor is formed into an island shape, and Mo is used as an electrode.
/ Ta and other conductive films are formed and patterned to
And the drain electrode 40 is formed. In this case, the source and drain electrodes 40 are formed so as to cover a part of the channel protection film 6.

As the conductive film, a transparent conductive film such as ITO can be used. In this embodiment, it is this conductive film that contacts the semiconductor in the source and drain regions.
In this case as well, the contact resistance between the n ⁺ μc-Si layer 7 and the source / drain electrode 40 can be reduced, and an effect similar to that of the first embodiment can be obtained.

Although the silicon film is used in the above embodiments, the present invention is not limited to this, and SiGe or Ge may be used. Further, in the above embodiments, the MOS type gate electrode in which the gate insulating film is formed on the gate metal is used, but a gate electrode structure other than this, for example, a silicon film is formed on the Schottky metal. The Schottky type gate electrode may be used.

Further, a silicon nitride film serving as a passivation film may be formed on the entire TFT, or an organic or inorganic black matrix layer for shielding light may be further patterned thereon. Examples of the organic black matrix used here include those in which an organic pigment is dissolved in an acrylic resin.

Depending on the film formation conditions of the passivation film, fixed charges and interface levels may be generated, and the inclination of the Id-Vgs characteristics in the subthreshold region may become small. Μc-
Since there is Si, good Id-Vgs characteristics can be obtained regardless of the film formation conditions of the passivation film.

Although the n-channel TFT is formed in the above embodiment, a p-channel TFT can be formed. Further, in the above embodiments, a so-called inverted staggered TFT in which the gate electrode is formed on the substrate was prepared, but the present invention can also be applied to a staggered TFT in which the gate electrode is on top. Besides, various modifications can be made without departing from the spirit of the present invention.

[0033]

As described above, according to the present invention, it is possible to provide a thin film transistor which has a high driving capability and operates at high speed even if the channel length is shortened.

[Brief description of drawings]

FIG. 1 is a sectional view of a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a top view of the thin film transistor according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of the thin film transistor according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a thin film transistor according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a conventional thin film transistor.

[Explanation of symbols]

1: Glass substrate 2: Gate metal 3: Gate insulating film 4: Amorphous silicon layer 5: Crystal silicon layer 6: Channel protective film 7: n ⁺ amorphous silicon layer 8: n ⁺ crystalline silicon layer 9: Silicide layer 10: Source and drain electrodes

Claims (2)

[Claims] 1. A gate electrode, a channel region provided in contact with the gate electrode, a source region and a drain region provided in contact with the channel region, and a source region and a drain region. In a thin film transistor having two wiring electrodes provided in contact with each other, the channel region, the source region and the drain region are made of an amorphous semiconductor, and the wiring region of the source region and the drain region is used. A thin film transistor characterized in that a surface portion connected to an electrode is composed of a semiconductor containing crystals. 2. A gate electrode, a channel region provided on and in contact with the gate electrode, a source region and a drain region provided adjacent to the channel region, and in contact with the channel region. The channel protection film provided and the source
In a thin film transistor including two wiring electrodes provided in contact with a source region and a drain region, the channel region, the source region and the drain region are made of an amorphous semiconductor, and the source region and A thin film transistor characterized in that a surface portion of the drain region connected to the wiring electrode and a surface portion of the channel region connected to the channel protective film are made of a semiconductor containing crystals.