KR950004585A - Manufacturing method of self-aligning thin film transistor - Google Patents

Abstract

The present invention relates to a method of manufacturing a self-aligning thin film transistor, and in particular, to form the overlap between the gate electrode and the source / drain electrode of polycrystalline silicon and the channel portion of amorphous silicon to improve the characteristics and performance of the device The present invention relates to a method of manufacturing a self-aligning thin film transistor for the purpose of forming a gate electrode by depositing and patterning a metal on an insulating glass substrate, and forming an anodized insulating film on the gate electrode. Forming a channel protective layer by successively depositing a gate insulating layer, an amorphous silicon layer, and a channel protective layer on the anodization insulating film, applying a positive photoresist film on the channel protective layer, and patterning the same; Converts the amorphous silicon layer in which the channel protection layer is not formed into a polycrystalline silicon layer, Group is achieved by manufacturing the thin film transistor to the step of forming the source / drain electrodes on a polycrystalline silicon layer.

Description

Manufacturing method of self-aligning thin film transistor

Since this is an open matter, no full text was included.

3 is a cross-sectional view of a self-aligning thin film transistor according to the present invention, FIG. 4 is a manufacturing process diagram of the self-aligning thin film transistor of FIG.

Claims (10)

Depositing and patterning a metal on an insulating glass substrate to form a gate electrode, and forming an anodized insulating film on the gate electrode, and successively forming a gate insulating layer, an amorphous silicon layer, and a channel protective layer on the anodized insulating film. Depositing sequentially, applying a positive photoresist film on the channel protection layer, and then patterning to form a channel protection layer; converting the amorphous silicon layer in which the channel protection layer is not formed into a polycrystalline silicon layer, and forming an upper portion of the polycrystalline silicon layer A method of manufacturing a self-aligning thin film transistor, characterized in that the step of forming a source / drain electrode in the. The method of claim 1, wherein the channel protective layer is formed by irradiating ultraviolet rays from the back surface of the insulating glass substrate. The method of manufacturing a self-aligning thin film transistor according to claim 1, wherein the channel protective layer has a thickness of about 0.5 to 1 mu m. The method of claim 1, wherein the width of the channel protection layer is formed to be narrower than that of the gate electrode. The method of manufacturing a self-aligning thin film transistor according to claim 2, wherein the ultraviolet irradiation dose is 50mw / cm ² . 6. The method of manufacturing a self-aligning thin film transistor according to claim 2 or 5, wherein the ultraviolet light is exposed for about 1 minute. The method of manufacturing a self-aligning thin film transistor according to claim 1, wherein the polycrystalline silicon layer is formed of an amorphous silicon layer in which the channel protective layer is not patterned. The method of manufacturing a self-aligning thin film transistor according to claim 1, wherein the polycrystalline silicon layer is formed on the amorphous silicon layer by a long wavelength XeF laser annealing process. The method of manufacturing a self-aligning thin film transistor according to claim 1, wherein the polycrystalline silicon layer is formed on the amorphous silicon layer with a long wavelength ArF laser. The method of manufacturing a self-aligning thin film transistor according to claim 1, wherein the polycrystalline silicon layer is formed of an n-type polycrystalline silicon layer by doping impurities. ※ Note: The disclosure is based on the initial application.