JPS5643743A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5643743A
JPS5643743A JP11900979A JP11900979A JPS5643743A JP S5643743 A JPS5643743 A JP S5643743A JP 11900979 A JP11900979 A JP 11900979A JP 11900979 A JP11900979 A JP 11900979A JP S5643743 A JPS5643743 A JP S5643743A
Authority
JP
Japan
Prior art keywords
layer
wiring
lower layer
lowering
built
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11900979A
Other languages
Japanese (ja)
Inventor
Toshio Kurahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11900979A priority Critical patent/JPS5643743A/en
Publication of JPS5643743A publication Critical patent/JPS5643743A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Abstract

PURPOSE:To prevent the lowering of dielectric strength among wirings by a method wherein a lower layer wiring, whose surface has an insulating film, is formed on a substrate, a silicon hydroxide is applied on the whole surface and the surface is heated and a silicon oxide layer is made up, and an upper layer wiring is built up through an insulating film, in the formation of a multilayer wiring. CONSTITUTION:A metallic layer 1' for lower layer wiring in Al is formed on an Si substrate 2 on which a function element 6 is made up, an SiO2 film 7 is built up on the surface, patterning is conducted, and the lower layer Al wiring 1 is formed. A liquid 3 obtained by dissolving a silicon hydroxide such as Si(OH)4 or its low molecular polymer in ethanol, etc. is applied, heated and dehydrated and condensed, and an SiO2 layer 3 covering the lower layer wiring is made up. The upper layer Al wiring 5 is formed on the layer 3 through an interphase insulating layer 4 such as a phosphor silicate glass layer 4. Thus, the generation of cracks in the interphase insulating layer and the growth of hillocks formed on the lower layer wiring are prevented, and the lowering of dielectric strength can be prevented.
JP11900979A 1979-09-17 1979-09-17 Manufacture of semiconductor device Pending JPS5643743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11900979A JPS5643743A (en) 1979-09-17 1979-09-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11900979A JPS5643743A (en) 1979-09-17 1979-09-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5643743A true JPS5643743A (en) 1981-04-22

Family

ID=14750725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11900979A Pending JPS5643743A (en) 1979-09-17 1979-09-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5643743A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888212B2 (en) * 1997-08-22 2005-05-03 Micron Technology, Inc. Method for trench isolation by selective deposition of low temperature oxide films

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4852185A (en) * 1971-10-29 1973-07-21
JPS4933232A (en) * 1972-07-28 1974-03-27
JPS5212588A (en) * 1975-07-21 1977-01-31 Hitachi Ltd Production method of semi-conductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4852185A (en) * 1971-10-29 1973-07-21
JPS4933232A (en) * 1972-07-28 1974-03-27
JPS5212588A (en) * 1975-07-21 1977-01-31 Hitachi Ltd Production method of semi-conductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6888212B2 (en) * 1997-08-22 2005-05-03 Micron Technology, Inc. Method for trench isolation by selective deposition of low temperature oxide films

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