KR970003856A - Method of forming contact hole in manufacturing semiconductor device - Google Patents

Method of forming contact hole in manufacturing semiconductor device Download PDF

Info

Publication number
KR970003856A
KR970003856A KR1019950019081A KR19950019081A KR970003856A KR 970003856 A KR970003856 A KR 970003856A KR 1019950019081 A KR1019950019081 A KR 1019950019081A KR 19950019081 A KR19950019081 A KR 19950019081A KR 970003856 A KR970003856 A KR 970003856A
Authority
KR
South Korea
Prior art keywords
forming
insulating layer
contact hole
layer
pattern
Prior art date
Application number
KR1019950019081A
Other languages
Korean (ko)
Inventor
정의삼
김대희
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950019081A priority Critical patent/KR970003856A/en
Publication of KR970003856A publication Critical patent/KR970003856A/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 예정된 패턴(12)이 형성된 반도체 기판(11)상에 하부층과의 절연을 위해 절연층(13)을 형성하는 단계를 포함하는 콘택홀 형성 방법에 있어서, 상기 절연층(13) 상에 콘택홀을 형성하기 위한 감광층(14) 패턴을 형성한 다음, 상기 절연층의 노출부위를 일정 깊이 식각하는 제1단계; 상기 감광층 패턴을 부분 식각하여 상기 절연층의 모서리 부분을 일부 노출시키는 제2단계; 예정된 콘택부분이 노출될 때까지 상기 절연층을 대해 시각공정을 수행하는 제3단계; 및 상기 절연층의 측벽에 산화층 스페이서(15′)를 형성하는 제4단계를 포함하는 것을 특징으로 하는 콘택홀 형성 방법에 관한 것으로, 마스크 오정렬에 의한 쇼트문제를 보상할 수 있고, 이에 따라 소자의 전기적 특성 및 제조수율을 향상 시킬 수 있도록 한 것이다.The present invention provides a method for forming a contact hole comprising forming an insulating layer (13) for insulation with a lower layer on a semiconductor substrate (11) on which a predetermined pattern (12) is formed. A first step of forming a photoresist layer 14 pattern for forming a contact hole and then etching an exposed portion of the insulating layer to a predetermined depth; Partially etching the photosensitive layer pattern to partially expose edge portions of the insulating layer; Performing a visual process on the insulating layer until a predetermined contact portion is exposed; And a fourth step of forming an oxide layer spacer 15 ′ on the sidewalls of the insulating layer. The contact hole forming method may compensate for a short problem due to mask misalignment. It is to improve the electrical characteristics and manufacturing yield.

Description

반도체 소자 제조시 콘택홀 형성 방법Method of forming contact hole in manufacturing semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3D도는 본 발명에 따른 콘택 과정을 설명하는 설명도.3D is an explanatory diagram illustrating a contact process according to the present invention.

Claims (8)

예정된 패턴이 형성된 반도체 기판상에 하부층과의 절연을 위해 절연층을 형성하는 단계를 포함하는 콘택홀 형성 방법에 있어서, 상기 절연층 상의 콘택홀을 형성하기 위한 감광층 패턴을 형성한 다음, 상기 절연층의 노출부위를 일정 깊이 식각하는 제1단계; 상기 감광층 패턴을 부분 식각하여 상기 절연층의 모서리 부분을 일부 노출시키는 제2단계; 예정된 콘택부분이 노출될 때까지 상기 절연층에 대해 식각공정을 수행하는 제3단계를 포함하는 것을 특징으로 하는 콘택홀 형성 방법.A method for forming a contact hole, the method comprising: forming an insulating layer to insulate an underlying layer on a semiconductor substrate on which a predetermined pattern is formed, wherein the photosensitive layer pattern for forming a contact hole on the insulating layer is formed, and then the insulation is formed. A first step of etching the exposed portion of the layer to a predetermined depth; Partially etching the photosensitive layer pattern to partially expose edge portions of the insulating layer; And performing a etching process on the insulating layer until a predetermined contact portion is exposed. 제1항에 있어서, 상기 제3단계 수행 후 상기 절연층의 측벽에 산화층 스페이서를 형성하는 제4단계를 더 포함하는 것을 특징으로 하는 콘택홀 형성 방법.The method of claim 1, further comprising: forming an oxide layer spacer on sidewalls of the insulating layer after performing the third step. 제1항 또는 제2항에 있어서, 상기 제1단계는 CF 개스를 이용하여 상기 절연층의 노출부위를 일정 깊이 제거하도록 수행되는 것을 특징으로 하는 콘택홀 형성 방법.3. The method of claim 1, wherein the first step is performed to remove a predetermined depth of the exposed portion of the insulating layer using CF gas. 4. 제1항 또는 제2항에 있어서, 상기 제2단계는 PET(Post Etch Treatmemnt)공정을 이용하여 수행되는 것을 특징으로 하는 콘택홀 형성 방법.The method of claim 1, wherein the second step is performed by using a post etching treatment (PET) process. 제4항에 있어서, 상기 PET 공정은 O2개스 또는 O2/CF4개스중 어느 하나를 소스개스로 사용하여 수행되는 것을 특징으로 하는 콘택홀 형성 방법.The method of claim 4, wherein the PET process is performed using any one of O 2 gas or O 2 / CF 4 gas as the source gas. 제5항에 있어서, 상기 PET 공정은 상기 소스개스의 개스량을 50 내지 130sccm, 소정 패턴이 형성되어 있는 상기 반도체 기판의 상부 온도를 240 내지 280℃, 바이어스 파워를 2600 내지 3000W, 소스 파워를 100 내지 500W로 각각 설정하여 수행되는 것을 특징으로 하는 콘택홀 형성 방법.The method of claim 5, wherein the PET process is the amount of gas of the source gas 50 to 130sccm, the upper temperature of the semiconductor substrate on which a predetermined pattern is formed 240 to 280 ℃, bias power 2600 to 3000W, source power 100 Contact hole forming method characterized in that is performed by setting to each to 500W. 제6항에 있어서, 상기 PET공정은 소정 패턴이 형성되어 있는 상기 반도체 기판의 측면 온도를 200 내지 240℃, 소정 패턴이 형성되어 있는 상기 반도체 기판의 하부 온도(척의 온도)를 -20내지 0℃로 설정하여 수행되는 것을 특징으로 하는 콘택홀 형성 방법.The method of claim 6, wherein the PET process is a side temperature of the semiconductor substrate on which a predetermined pattern is formed is 200 to 240 ℃, the lower temperature (temperature of the chuck) of the semiconductor substrate on which a predetermined pattern is formed -20 to 0 ℃ Method for forming a contact hole, characterized in that carried out by setting to. 제4항에 있어서, 상기 PET 공정은 인-시튜(in-situ)로 수행되는 것을 특징으로 하는 콘택홀 형성 방법.The method of claim 4, wherein the PET process is performed in-situ. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019081A 1995-06-30 1995-06-30 Method of forming contact hole in manufacturing semiconductor device KR970003856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019081A KR970003856A (en) 1995-06-30 1995-06-30 Method of forming contact hole in manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019081A KR970003856A (en) 1995-06-30 1995-06-30 Method of forming contact hole in manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR970003856A true KR970003856A (en) 1997-01-29

Family

ID=66526205

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950019081A KR970003856A (en) 1995-06-30 1995-06-30 Method of forming contact hole in manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR970003856A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100720485B1 (en) * 2005-12-28 2007-05-22 동부일렉트로닉스 주식회사 Method of fabricating copper metal line of the semiconductor device
KR200492749Y1 (en) 2019-06-18 2020-12-04 주식회사 엠엔디코리아 Dry Plate With Enhanced Air Permeability

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100720485B1 (en) * 2005-12-28 2007-05-22 동부일렉트로닉스 주식회사 Method of fabricating copper metal line of the semiconductor device
KR200492749Y1 (en) 2019-06-18 2020-12-04 주식회사 엠엔디코리아 Dry Plate With Enhanced Air Permeability

Similar Documents

Publication Publication Date Title
KR940006280A (en) Semiconductor device, manufacturing method thereof, and manufacturing method of silicon insulating substrate
KR950001901A (en) Contact hole manufacturing method
KR970003856A (en) Method of forming contact hole in manufacturing semiconductor device
KR960005943A (en) Isolation Method of Semiconductor Devices
KR970052384A (en) Method for forming contact hole in semiconductor device
KR960026459A (en) Transistor Manufacturing Method
KR960039285A (en) Semiconductor device manufacturing method
KR100642477B1 (en) Method for fabricating Align Key of the semiconductor device
KR100358174B1 (en) Method for forming source and drain of semiconductor device
KR940002966A (en) Method of removing interlayer short circuit by polysilicon etching residue
KR960005793A (en) Mask rom and method of making the same.
KR970003507A (en) Contact hole formation method of semiconductor device
KR970023714A (en) Contact portion of semiconductor device and forming method thereof
KR970003496A (en) Method of forming micro contact hole in manufacturing semiconductor device
KR970052248A (en) Contact hole formation method of semiconductor device
KR940001408A (en) Semiconductor cell manufacturing method
KR960002569A (en) How to Form Metal Wiring Alignment Keys
KR970052349A (en) Metal wiring formation method of semiconductor device
KR950015599A (en) Method for forming contact region of semiconductor device
KR960035901A (en) Gate electrode formation method
KR970052621A (en) Manufacturing Method of Semiconductor Device
KR970052508A (en) Contact hole formation method of semiconductor device
KR960005791A (en) Contact hole formation method of semiconductor device
KR960012324A (en) Gate electrode contact of semiconductor device and manufacturing method thereof
KR970030805A (en) Nonvolatile Memory Device and Manufacturing Method Thereof

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination