KR950015599A - Method for forming contact region of semiconductor device - Google Patents

Method for forming contact region of semiconductor device Download PDF

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Publication number
KR950015599A
KR950015599A KR1019930025141A KR930025141A KR950015599A KR 950015599 A KR950015599 A KR 950015599A KR 1019930025141 A KR1019930025141 A KR 1019930025141A KR 930025141 A KR930025141 A KR 930025141A KR 950015599 A KR950015599 A KR 950015599A
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South Korea
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region
semiconductor device
contact
forming
semiconductor
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KR1019930025141A
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Korean (ko)
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KR100306901B1 (en
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박주석
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문정환
금성일렉트론 주식회사
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Priority to KR1019930025141A priority Critical patent/KR100306901B1/en
Publication of KR950015599A publication Critical patent/KR950015599A/en
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Publication of KR100306901B1 publication Critical patent/KR100306901B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 장치의 접촉영역의 형성을 위한 방법에 관한 것으로, 특히 미세소자의 형성에 따른 협소한 영역의 접촉영역형성시 소자의 전기적 특성악화를 개선하도록 한 반도체 장치의 접촉영역 형성방법에 관한 것으로, 비활성 영역으로 포위된 화성영역상에 형성된 반도체 장치의 접촉영역상에 도전층을 연결하기 위한 접촉영역을 형성하는 반도체 장치의 접촉 영역 형성방법에 있어서, 상기 반도체 장치 전면에 형성한 절연층상에 상기 접촉 영역을 위한 접촉창을 사진식각 방법으로 형성하여 반도체 장치의 앨 영역을 노출시키는 단계와: 상기 노출된 반도체 영역에 대해 이온 주입을 행하는 단계와; 상기 이온 주입후 상기 형성된 접촉창에 도전층을 형성하여 연결하는 단계로 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming a contact region of a semiconductor device, and more particularly, to a method for forming a contact region of a semiconductor device to improve the deterioration of electrical characteristics of a device when forming a contact region of a narrow region due to the formation of a microelement. A method for forming a contact region of a semiconductor device, the method comprising forming a contact region for connecting a conductive layer on a contact region of a semiconductor device formed on a chemical conversion region surrounded by an inactive region. Forming a contact window for the contact region by a photolithography method to expose the AL region of the semiconductor device, and performing ion implantation on the exposed semiconductor region; Forming and connecting a conductive layer to the formed contact window after the ion implantation.

Description

반도체 장치의 접촉 영역 형성 방법Method for forming contact region of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도(a) 내지 제3도(e)는 본 발명의 공정을 나타낸 공정도, 제4도는 본 발명에 따른 소자의 전기적특성을 종래와 비교하여 나타낸 그래프이다.3 (a) to 3 (e) are process charts showing the process of the present invention, and FIG. 4 is a graph showing the electrical characteristics of the device according to the present invention in comparison with the prior art.

Claims (5)

비활성 영역으로 포위된 활성영역상에 형성된 반도체 장치의 접촉영역상에 도전층을 연결하기 위한 접촉영역을 형성하는 반도체 장치의 접촉영역 형성 방법에 있어서. 상기 반도체 장치 전면에 형성한 절연층상에 상기 접촉영역을 위한 접촉창을 사진식각 방법으로 형성하여 반도체 장치의 앨 영역을 노출시키는 단계와: 상기 노출된 반도체 영역에 대해 이온 주입을 행하는 단계와; 상기 이온 주입후 상기 형성된 접촉창에 도전층을 형성하여 연결하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치의 접촉영역 형성방법.A method for forming a contact region of a semiconductor device, comprising forming a contact region for connecting a conductive layer on a contact region of a semiconductor device formed on an active region surrounded by an inactive region. Exposing an AL region of the semiconductor device by forming a contact window for the contact region on the insulating layer formed on the entire surface of the semiconductor device by a photolithography method, and performing ion implantation on the exposed semiconductor region; And forming a conductive layer in the contact window formed after the ion implantation and connecting the conductive layer. 제1항에 있어서, 상기 접촉되는 반도체 영역은 접촉창 형성을 위해 사진 식각시 비환성 영역의 식각에 의해 노출된 반도체 층을 포함하는 것을 특징으로 하는 반도체 장치의 접촉영역 형성방법.The method of claim 1, wherein the contacting semiconductor region comprises a semiconductor layer exposed by etching of an acyclic region during photolithography to form a contact window. 제3항에 있어서, 상기 반도체 장치는 기억장치에 적합한 MOS트랜지스터이며 상기 접촉되는 반도체 영역은 MOS트랜지스터의 소오스 영역이거나 또는 비활성영역의 식각에 의해 노출된 반도체 층을 포함한 소오스 영역인 것을 특징으로 하는 반도체 장치의 접촉영역 형성방법.The semiconductor device of claim 3, wherein the semiconductor device is a MOS transistor suitable for a storage device, and the semiconductor region to be contacted is a source region of the MOS transistor or a source region including a semiconductor layer exposed by etching of an inactive region. Method for forming a contact area of a device. 제1항에 있어서, 상기 접촉창 형성후 이온 주입은 접촉되는 반도체 영역과 동일도전형의 불순물을 30 내지 40keV, 1x1013내지 3×1013ions/㎤로 형성함을 특징으로 하는 반도체 장치의 접촉영역 형성방법.The method of claim 1, wherein the contact of the semiconductor device, characterized in that the said contact window, to form the ion implantation is formed in the semiconductor region and the same is also typical of the impurities from 30 to 40keV, 1x10 13 to 3 × 10 13 ions / ㎤ contacting Zone Formation Method. 제1항에 있어서, 상기 형성된 접촉창에 도전층은 다결정실리콘으로 형성됨을 특징으로 하는 반도체 장치의 접촉영역 형성방법.The method of claim 1, wherein a conductive layer is formed of polycrystalline silicon in the formed contact window. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930025141A 1993-11-24 1993-11-24 Method for forming contact hole of semiconductor device KR100306901B1 (en)

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KR1019930025141A KR100306901B1 (en) 1993-11-24 1993-11-24 Method for forming contact hole of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019930025141A KR100306901B1 (en) 1993-11-24 1993-11-24 Method for forming contact hole of semiconductor device

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KR950015599A true KR950015599A (en) 1995-06-17
KR100306901B1 KR100306901B1 (en) 2001-11-30

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