KR19980037176A - Method of forming interlayer insulating film of semiconductor device - Google Patents
Method of forming interlayer insulating film of semiconductor device Download PDFInfo
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- KR19980037176A KR19980037176A KR1019960055892A KR19960055892A KR19980037176A KR 19980037176 A KR19980037176 A KR 19980037176A KR 1019960055892 A KR1019960055892 A KR 1019960055892A KR 19960055892 A KR19960055892 A KR 19960055892A KR 19980037176 A KR19980037176 A KR 19980037176A
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자의 SOG막과 층간절연막 형성시, SOG막과 층간절연막을 인시투(In-Situ)진행을 함으로써 SOG막의 열처리로 발생되는 결함을 개선하고, 층간절연막 형성시 지연시간을 단축하여 안정도를 높인 반도체 소자의 층간절연막 형성방법이 개시된다.When SOG film and interlayer insulating film are formed in semiconductor device, SOG film and interlayer insulating film are processed in-situ to improve defects caused by heat treatment of SOG film and to improve stability by shortening delay time when forming interlayer insulating film. A method of forming an interlayer insulating film of a semiconductor device is disclosed.
Description
본 발명은 다중 금속 배선 구조를 갖는 반도체 소자의 금속 층간절연막 형성방법에 관한 것으로, 특히 표면 평탄화에 사용되는 SOG막과 층간절연막을 형성하는 일련의 공정을 단축시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal interlayer insulating film of a semiconductor device having a multi-metal wiring structure, and more particularly, to a method for shortening a series of processes for forming an SOG film and an interlayer insulating film used for surface planarization.
종래 반도체 제조공정에서, 금속 배선간의 절연을 위해 제 1 층간절연막을 형성한 다음 표면의 평탄화를 위해 SOG막과 제 2 층간 절연막이 순차적으로 형성하게 된다. 그런데 상기 SOG막을 형성하는데 있어서, 실리콘기판에 SOG 용액을 도포한 다음 튜브(Tube) 내에서 장시간 열처리 공정을 실시하게 된다. 이때 장시간의 열처리로 인하여 실리콘기판에 결함(Crack)이 발생하기 쉽다. 그리고 상기 열처리 공정 후, 제 2 층간절연막을 형성하기 위하여 다른 챔버로 이동하는 사이에 공기중에 노출된 SOG막은 수분을 흡수하게 된다. 그후 상기 수분을 흡수한 SOG막 상에 제 2 층간 절연막을 형성하게 되면 소자의 안정도가 떨어지는 문제가 발생하게 된다.In a conventional semiconductor manufacturing process, the first interlayer insulating film is formed to insulate metal wirings, and then the SOG film and the second interlayer insulating film are sequentially formed to planarize the surface. However, in forming the SOG film, the SOG solution is applied to a silicon substrate, and then a long heat treatment process is performed in a tube. At this time, cracks are likely to occur in the silicon substrate due to prolonged heat treatment. After the heat treatment process, the SOG film exposed to air while moving to another chamber to form the second interlayer insulating film absorbs moisture. Subsequently, when the second interlayer insulating film is formed on the SOG film absorbing the moisture, the stability of the device may be deteriorated.
따라서 본 발명은 SOG막과 제 2 층간절연막을 형성시, 다중챔버내에서 두 공정을 동시에 실시하는 인시투(In-situ)진행으로 상술한 문제점을 해결할 수 있는 반도체 소자의 금속층간 절연막 형성 방법을 제공하는데 목적이 있다.Accordingly, the present invention provides a method for forming an interlayer insulating film of a semiconductor device, which can solve the above-mentioned problems by performing an in-situ process of simultaneously performing two processes in multiple chambers when forming an SOG film and a second interlayer insulating film. The purpose is to provide.
상기 목적을 달성하기 위한 본 발명의 금속 층간절연막 형성 방법은 실리콘 기판에 형성되며 패터닝 된 금속층이 형성되는 단계와, 상기 단계로부터 제 1 층간 절연막을 형성하는 단계와, 상기 단계로부터 챔버내에서 SOG용액을 도포하는 단계와, 상기 단계로부터 상기 챔버내에서 상기 SOG용액을 열처리하여 SOG막을 형성하는 단계와, 상기 단계로부터 상기 챔버내에서 제 2 층간절연막을 형성하는 단계로 이루어지는 반도체 소자의 층간 절연막 형성방법에 있어서, 상기 SOG용액의 열처리 및 상기 제 2 층간절연막 형성공정은 인시투 공정으로 실시되는 것을 특징으로 한다.In order to achieve the above object, the method for forming a metal interlayer dielectric film of the present invention comprises forming a patterned metal layer on a silicon substrate, forming a first interlayer dielectric film from the step, and SOG solution in the chamber from the step. Forming a SOG film by heat-treating the SOG solution in the chamber from the step; and forming a second interlayer insulating film in the chamber from the step. The heat treatment of the SOG solution and the process of forming the second interlayer dielectric film are performed in an in-situ process.
도 1A 내지 도 1B는 본 발명에 따라 반도체 소자의 층간절연막을 형성하는 방법을 설명하기 위한 단면도.1A to 1B are cross-sectional views for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘기판2 : 금속층1: silicon substrate 2: metal layer
3 : 제 1 층간절연막4 : SOG막3: first interlayer insulating film 4: SOG film
5 : 제 2 층간절연막5: second interlayer insulating film
이하, 본 발명을 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.
도 1A 내지 도 1B는 본 발명에 따른 반도체 소자의 층간절연 및 평탄화 방법을 설명하기 위한 소자의 단면도이다.1A to 1B are cross-sectional views of devices for explaining an interlayer insulating and planarization method of a semiconductor device according to the present invention.
도 1A는 실리콘기판(1)상에 패턴닝된 금속층(2) 및 제 1 층간 절연막(3)을 형성한 상태를 도시한다.FIG. 1A shows a state where a patterned metal layer 2 and a first interlayer insulating film 3 are formed on a silicon substrate 1.
도 1B는 제 1 층간절연막(3) 전체 상부에 SOG막(4) 및 제 2 층간절연막(5)을 형성한 상태를 도시한다. 이때 다중챔버 내에서 상기 SOG막(4)을 형성하기 위하여 SOG용액을 열처리하는 공정과 상기 제 2 층간절연막(5)을 형성하는 두 공정이 인시투 진행을 한다.FIG. 1B shows a state in which the SOG film 4 and the second interlayer insulating film 5 are formed over the entire first interlayer insulating film 3. In this case, two processes of heat treating the SOG solution and forming the second interlayer insulating film 5 to form the SOG film 4 in the multiple chamber are performed in-situ.
상술한 바와 같이 본 발명에 의하면 단일 다중 챔버 내에서 SOG막 및 제 2 층간절연막 형성을 인시투 진행을 함으로써, 공정이 간소화되고 소자가 공기에 노출이 되지 않게 된다. 따라서 생산시간 단축, 소자의 안정성 개선 및 열공정으로 인한 결함이 억제되는 등의 효과가 있다.As described above, according to the present invention, the SOG film and the second interlayer insulating film are formed in-situ in a single multiple chamber, thereby simplifying the process and preventing the device from being exposed to air. Therefore, there is an effect such as shortening the production time, improving the stability of the device and suppressed defects due to the thermal process.
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KR1019960055892A KR19980037176A (en) | 1996-11-21 | 1996-11-21 | Method of forming interlayer insulating film of semiconductor device |
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KR1019960055892A KR19980037176A (en) | 1996-11-21 | 1996-11-21 | Method of forming interlayer insulating film of semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100315416B1 (en) * | 1999-01-22 | 2001-11-28 | 한신혁 | Method for forming collar oxide of tranch capacitor |
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1996
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100315416B1 (en) * | 1999-01-22 | 2001-11-28 | 한신혁 | Method for forming collar oxide of tranch capacitor |
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