KR970052853A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970052853A
KR970052853A KR1019950065621A KR19950065621A KR970052853A KR 970052853 A KR970052853 A KR 970052853A KR 1019950065621 A KR1019950065621 A KR 1019950065621A KR 19950065621 A KR19950065621 A KR 19950065621A KR 970052853 A KR970052853 A KR 970052853A
Authority
KR
South Korea
Prior art keywords
sog film
film
forming
insulating film
metal wiring
Prior art date
Application number
KR1019950065621A
Other languages
Korean (ko)
Other versions
KR100199344B1 (en
Inventor
정창원
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950065621A priority Critical patent/KR100199344B1/en
Publication of KR970052853A publication Critical patent/KR970052853A/en
Application granted granted Critical
Publication of KR100199344B1 publication Critical patent/KR100199344B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다중 금속 배선 구조에서 금속층간 절연막에 적용되는 SOG막의 막질을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법이 개시된다.The present invention discloses a method of manufacturing a semiconductor device capable of improving the reliability of the device by improving the film quality of the SOG film applied to the interlayer insulating film in a multi-metal wiring structure.

본 발명은 다층구조의 금속층간 절연막중 SOG막을 도포한 후, SOG막내의 수분을 제거하기 위한 공정을 실시하고, 인 이온을 SOG막의 표면에 주입하고, 상부 금속배선 형성공정전에 다시 한번 SOG막내의 수분을 제거하는 공정을 실시한다.According to the present invention, after applying the SOG film in the interlayer insulating film of the multi-layer structure, a process for removing moisture in the SOG film is carried out, the phosphorus ions are implanted into the surface of the SOG film, and once again before the upper metal wiring forming step Implement a process to remove moisture.

따라서, 본 발명은 금속층간 절연막에 적용되는 SOG막의 단점인 수분을 효과적으로 제거하므로써, 소자의 수율향상 및 신뢰성을 향상시킬 수 있다.Therefore, the present invention can improve the yield and reliability of the device by effectively removing moisture, which is a disadvantage of the SOG film applied to the interlayer insulating film.

* 선택도 : 제1A도.* Selectivity: Figure 1A.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A 및 1B도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (4)

반도체 소자의 제조방법에 있어서, 하부 금속배선이 형성된 실리콘 기판이 제공되고, 상기 하부 금속배선을 포함한 전체구조상에 제1절연막이 형성되는 단계; 상기 제1절연막상에 SOG막을 도포한 후, 상기 SOG막에 함유된 수분을 제거하기 위한 열처리공정이 실시되는 단계; 인(P) 이온주입공정을 실시함에 의해 상기 SOG막의 표면에 인 이온 주입층을 형성한 후, 상기 SOG막상에 제2절연막이 형성되는 단계; 및 비아 콘택홀 형성공정후 프리-히팅하고, 이후 상부 금속배선이 형성되는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, comprising: providing a silicon substrate on which a lower metal wiring is formed, and forming a first insulating film on the entire structure including the lower metal wiring; Applying a SOG film on the first insulating film, and then performing a heat treatment process to remove moisture contained in the SOG film; Forming a phosphorus ion implantation layer on the surface of the SOG film by performing a phosphorus (P) ion implantation process, and then forming a second insulating film on the SOG film; And pre-heating after the via contact hole forming process, and then forming an upper metal wiring. 제1항에 있어서, 상기 열처리공정은 1차로 320℃ 온도에서 2분간 베이킹하고, 2차로 360 내지 440℃의 온도범위에서 60분간 큐링하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the heat treatment process is performed by first baking at 320 ° C. for 2 minutes and secondly curing at a temperature range of 360 to 440 ° C. for 60 minutes. 제1항에 있어서, 상기 프리-히팅은 250 내지 350℃의 온도범위에서 60 내지 100초간 실시되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the pre-heating is performed at a temperature in a range of 250 to 350 ° C. for 60 to 100 seconds. 제1항에 있어서, 상기 제1 및 제2절연막은 TEOS계 산화막인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first and second insulating films are TEOS oxide films. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065621A 1995-12-29 1995-12-29 Method of forming semiconductor device KR100199344B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065621A KR100199344B1 (en) 1995-12-29 1995-12-29 Method of forming semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065621A KR100199344B1 (en) 1995-12-29 1995-12-29 Method of forming semiconductor device

Publications (2)

Publication Number Publication Date
KR970052853A true KR970052853A (en) 1997-07-29
KR100199344B1 KR100199344B1 (en) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065621A KR100199344B1 (en) 1995-12-29 1995-12-29 Method of forming semiconductor device

Country Status (1)

Country Link
KR (1) KR100199344B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100231848B1 (en) * 1995-12-19 1999-12-01 김영환 Method for improving characteristics of sog

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100231848B1 (en) * 1995-12-19 1999-12-01 김영환 Method for improving characteristics of sog

Also Published As

Publication number Publication date
KR100199344B1 (en) 1999-06-15

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