KR100199344B1 - Method of forming semiconductor device - Google Patents
Method of forming semiconductor device Download PDFInfo
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- KR100199344B1 KR100199344B1 KR1019950065621A KR19950065621A KR100199344B1 KR 100199344 B1 KR100199344 B1 KR 100199344B1 KR 1019950065621 A KR1019950065621 A KR 1019950065621A KR 19950065621 A KR19950065621 A KR 19950065621A KR 100199344 B1 KR100199344 B1 KR 100199344B1
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- film
- insulating film
- sog film
- sog
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 다중 금속배선 구조에서 금속층간 절연막에 적용되는 SOG막의 막질을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법이 개시된다Disclosed is a method of manufacturing a semiconductor device capable of improving device reliability by improving a film quality of an SOG film applied to an intermetallic insulating film in a multi-metal interconnection structure.
본 발명의 다층구조의 금속층간 절연막중 SOG막을도포한 후, SOG막내의 수분을 제거하기 위한 공정을 실시하고, 인 이온을 SOG막의 표면에 주입하고, 상부 금속배선 형성공정전에 다시한번 SOG막내의 수분을 제거하는 고정을 실시한다.After applying the SOG film in the interlayer insulating film of the multi-layered structure of the present invention, a step for removing moisture in the SOG film is carried out, phosphorus ions are injected into the surface of the SOG film, and once again in the SOG film before the upper metal wiring forming step. Fix to remove moisture.
따라서, 본 발명은 금속층간 절연막에 적용된 SOG막의 단점인 수분을 효과적으로 제거하므로써, 소자의 수율향상 및 신뢰성을 향상시킬 수 있다.Therefore, the present invention can improve the yield and reliability of the device by effectively removing moisture, which is a disadvantage of the SOG film applied to the interlayer insulating film.
Description
제1a 및 1b도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해도시한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 층간 절연막1 silicon substrate 2 interlayer insulating film
3 : 하부 금속배선 4 : 제1 절연막3: lower metal wiring 4: first insulating film
5 : SOG막 6 : 제2 절연막5: SOG film 6: second insulating film
7 : 베리어 금속층 8 : 상부 금속배선7: Barrier metal layer 8: Upper metal wiring
10 : 인 이온10: phosphorus ion
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다중 금속배선 구조에서 금속층간 절연막에 적용되는 SOG막의 막질을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving device reliability by improving a film quality of an SOG film applied to an intermetallic insulating film in a multi-metal wiring structure.
다중 금속배선 구조의 반도체 소자에서 하부 금속배선과 상부 금속배선사이를 절연하기 위하여 금속층간 절연막이 형성된다. 금속층간 절연막은 2개 이상의 절연층을 적층하여 형성되는데, 표면 평탄화를 향상시키기 위하여 SOG막이 포함되도록 한다. SOG막은 표면 평탄화 특성이 우수한 반면에 친수성이 강한 관계로 내부에 수분이 다량 함유되어 있기 때문에 이 수분이 추후 진행되는 열공정에 의해 주변의 다른층으로 확산될 경우 소자의 신뢰성을 저하시키는 요인으로 작용하게 된다. 따라서, SOG막을 형성한 후에는 반듯이 수분제거를 위한 열처리공정을 진행하게 되는데, 이때 SOG막의 표면에 크랙(crack)이 발생되고, 이로인하여 파티클이 다량 발생되어 소자의 신뢰성을 저하시키게 된다.In the semiconductor device having a multi-metal interconnection structure, an insulating interlayer metal layer is formed to insulate between the lower metal interconnection and the upper metal interconnection. The intermetallic insulating film is formed by stacking two or more insulating layers, so that the SOG film is included to improve surface planarization. The SOG film has excellent surface planarization characteristics but has a high hydrophilicity, and thus contains a large amount of moisture. Therefore, when the moisture is diffused to another layer around by a subsequent thermal process, it acts as a factor that lowers the reliability of the device. Done. Therefore, after the SOG film is formed, a heat treatment process for water removal is performed. At this time, cracks are generated on the surface of the SOG film, thereby generating a large amount of particles, thereby degrading the reliability of the device.
따라서, 본 발명은 금속층간 절연막에 적용되는 SOG막의 막질을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the reliability of the device by improving the film quality of the SOG film applied to the intermetallic insulating film.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 하부 금속배선이 형성된 실리콘 기판이 제공되고, 상기 하부 금속배선을 포함한 전체구조산에 제1 절연막이 형성되는 단계; 상기 제1 절연막상에 SOG막을도포한 후, 상기 SOG막에 함유된 수분을 제거하기 위한 열처리공정이 실시되는 단계; 인(P) 이온주입공정을 실시함에 의해 상기 SOG막의 표면에 인 이온 주입층을 형성한 후, 상기 SOG막상에 제2 절연막이 형성되는 단계; 및 비아 콘택홀형성공정후 프리-히팅하고, 이후 상부 금속배선이 형성되는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a silicon substrate on which a lower metal wiring is formed, and forming a first insulating film on an entire structure including the lower metal wiring; Applying an SOG film on the first insulating film, and then performing a heat treatment process to remove moisture contained in the SOG film; Forming a phosphorus ion implantation layer on the surface of the SOG film by performing a phosphorus ion implantation process, and then forming a second insulating film on the SOG film; And pre-heating the via contact hole forming process, and then forming an upper metal wiring.
이하, 본 발명을 첨부된도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a 및 1b도는 본 발명의 실시예에 의한 반도체 소자의 제조방법을 설명하기 위해도시한 소자의 단면도이다.1A and 1B are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device according to the embodiment of the present invention.
제1A도를 참조하면, 층간 절연막(2)이 실리콘 기판(1)상에 형서되고, 층간 절연막(2)상에는 금속배선공정을 통해 하부 금속배선(3)이 형성된다. 하부 금속배선(3)을 포함한 층간 절연막(2)상에 제1 절연막(4)이 형성된다. 표면 평탄화를 위해, SOG막(5)은 제1 절연막(4)상에도포된다. 제1 절연막(4)은 금속층간 절연막의 하부층으로서 PECVD방식에 의해 350 내지 450℃의 온도에서 TEOS계 산화막을 500 내지 1000Å의 두께로 증착하여 형성되며, 금속층간 절연막의 중간층인 SOG막(5)에 함유된 수분이 하부 금속배선(3)으로 침투되는 것을 방지한다. SOG막(5)내에 함유된 수분을 제거하기 위한 열처리공정 예를들어, 1차로 320℃온도에서 2분간 베이킹(baking)을 하고, 2차로 360 내지 440℃의 온도범위에서 60분간 큐링(curing)을 실시한다. 큐링후 SOG막(5)표면에 발생되는 크랙을 방지하기 위하여, 인(Phosphorous;P) 이온주입공정을 실시함에 의해 SOG막(5)의 표면에 인 이온주입층(10)이 형성된다.Referring to FIG. 1A, the interlayer insulating film 2 is formed on the silicon substrate 1, and the lower metal wiring 3 is formed on the interlayer insulating film 2 through a metal wiring process. The first insulating film 4 is formed on the interlayer insulating film 2 including the lower metal wiring 3. For surface planarization, the SOG film 5 is also coated on the first insulating film 4. The first insulating film 4 is formed by depositing a TEOS-based oxide film at a thickness of 500 to 1000 GPa at a temperature of 350 to 450 DEG C by a PECVD method as a lower layer of the intermetallic insulating film, and an SOG film 5 as an intermediate layer of the intermetallic insulating film. Moisture contained in is prevented from penetrating into the lower metal wiring (3). Heat treatment process for removing moisture contained in SOG film 5 For example, first baking at 320 ° C. for 2 minutes, and secondly curing at a temperature range of 360 to 440 ° C. for 60 minutes. Is carried out. In order to prevent cracks occurring on the surface of the SOG film 5 after curing, a phosphorus ion implantation layer 10 is formed on the surface of the SOG film 5 by performing a phosphorous (P) ion implantation process.
제1B도를 참조하면, 제2 절연막(6)은 SOG막(5)상에 형성되며, 이로인하여 제1 절연막(4), SOG막(5) 및 제2 절연막(6)으로 된 금속층간 절연막이 완성된다. 비아 콘택홀(via contact hole)형성공정후 250 내지 350℃의 온도범위에서 60 내지 100초간 프리-히팅(pre-heating)하여 다시한번 SOG막(5)내의 수분을 제거한다. 베리어 금속층(7) 및 상부 금속배선(8)은 제2 절연막(6)상에 형성된다.Referring to FIG. 1B, the second insulating film 6 is formed on the SOG film 5, whereby the interlayer insulating film made of the first insulating film 4, the SOG film 5 and the second insulating film 6 This is done. After the via contact hole forming process, pre-heating is performed for 60 to 100 seconds at a temperature range of 250 to 350 ° C to remove moisture in the SOG film 5 again. The barrier metal layer 7 and the upper metal wiring 8 are formed on the second insulating film 6.
상기에서, 제2 절연막(6)은 금속층간 절연막의 상부층으로서 PECVD방식에 의해 350 내지 450℃의 온도에서 TEOS계 산화막을 500 내지 1000Å의 두께로 증착하여 형성되며, 금속층간 절연막의 중간층인 SOG막(5)에 함유된 수분이 상부 금속배선(8)으로 침투되는 것을 방지한다.In the above description, the second insulating film 6 is formed by depositing a TEOS-based oxide film at a thickness of 500 to 1000 kPa by a PECVD method as an upper layer of the intermetallic insulating film, and is an intermediate layer of the intermetallic insulating film. Moisture contained in (5) is prevented from penetrating into the upper metal wiring (8).
상술한 바와같이 본 발명은 다층구조의 금속층간 절연막중 SOG막을도포한 후, SOG막내의 수분을 제거하기 위한 공정을 실시하고, 인 이온을 SOG막의 표면에 주입하고, 상부 금속배선 형성공정전에 다시한번 SOG막내의 수분을 제거하는 공정을 실시한다.As described above, in the present invention, after the SOG film is applied in the interlayer insulating film of a multilayer structure, a process for removing moisture in the SOG film is performed, the phosphorus ions are implanted into the surface of the SOG film, and again before the upper metal wiring forming process. One step is to remove the moisture in the SOG film.
따라서, 본 발명은 금속층간 절연막에 적용되는 SOG막의 단점인 수분을 효과적으로 제거하므로써, 소자의 수율향상 및 신뢰성을 향상시킬 수 있다.Therefore, the present invention can improve the yield and reliability of the device by effectively removing moisture, which is a disadvantage of the SOG film applied to the interlayer insulating film.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950065621A KR100199344B1 (en) | 1995-12-29 | 1995-12-29 | Method of forming semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950065621A KR100199344B1 (en) | 1995-12-29 | 1995-12-29 | Method of forming semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970052853A KR970052853A (en) | 1997-07-29 |
| KR100199344B1 true KR100199344B1 (en) | 1999-06-15 |
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| KR1019950065621A KR100199344B1 (en) | 1995-12-29 | 1995-12-29 | Method of forming semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100231848B1 (en) * | 1995-12-19 | 1999-12-01 | 김영환 | Method for improving characteristics of sog |
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| KR970052853A (en) | 1997-07-29 |
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