KR980006122A - Method for forming interlayer insulating film of semiconductor device - Google Patents

Method for forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR980006122A
KR980006122A KR1019960022813A KR19960022813A KR980006122A KR 980006122 A KR980006122 A KR 980006122A KR 1019960022813 A KR1019960022813 A KR 1019960022813A KR 19960022813 A KR19960022813 A KR 19960022813A KR 980006122 A KR980006122 A KR 980006122A
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KR
South Korea
Prior art keywords
interlayer insulating
film
insulating film
forming
semiconductor device
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KR1019960022813A
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Korean (ko)
Inventor
정창원
Original Assignee
김주용
현대전자산업주식회사
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Priority to KR1019960022813A priority Critical patent/KR980006122A/en
Publication of KR980006122A publication Critical patent/KR980006122A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자의 금속층간 절연막 형성 방법에 관한 것으로, 비아 홀(Via hole)내에서 수분과의 접촉으로 인한 금속층의 부식을 방지하기 위하여 SOG막을 형성한 후 상기 SOG막내에 함유된 수분을 완전히 제거하고, 상기 SOG막상에 수분 투과율이 높은 TEOS막을 형성하므로써 비아 홀내에서 수분과의 접촉으로 인한 상부 금속층의 부식이 방지된다. 따라서 소자의 신뢰성 및 수율이 증대될 수 있는 반도체 소자의 금속층간 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and after forming an SOG film to prevent corrosion of the metal layer due to contact with moisture in a via hole, the moisture contained in the SOG film is completely removed. By removing and forming a TEOS film having a high moisture permeability on the SOG film, corrosion of the upper metal layer due to contact with moisture in the via hole is prevented. Accordingly, the present invention relates to a method for forming an interlayer insulating film of a semiconductor device, which can increase the reliability and yield of the device.

Description

반도체 소자의 금속층간 절연막 형성 방법Method for forming interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도 내지 제1c도는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

Claims (8)

반도체 소자의 금속층간 절연막 형성 방법에 있어서, 절연층이 형성된 실리콘 기판상에 금속배선을 형성 한 후 전체 상부면에 제1금속층간 절연막을 형성하는 단계와, 상기 단계로부터 상기 제1금속층간 절연막상에 SOG막을 도포하여 표면을 평탄화시킨 후 상기 SOG막내에 함유된 수분을 제거하기 위하여 경화 및 소성 공정을 순차적으로 실시하는 단계와, 상기 단계로부터 외부로부터 흡수된 수분을 제거하기 위하여 열처리를 실시한 후 상기 SOG막상에 제2금속층간 절연막을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.A method of forming a metal interlayer insulating film of a semiconductor device, comprising: forming a first metal interlayer insulating film on an entire upper surface after forming a metal wiring on a silicon substrate on which an insulating layer is formed; Applying a SOG film to the surface to planarize the surface, and sequentially performing a curing and baking process to remove moisture contained in the SOG film, and performing heat treatment to remove moisture absorbed from the outside from the step. And forming a second interlayer insulating film on the SOG film. 제1항에 있어서, 상기 제1금속층간 절연막은 실리콘 리치 산화막인 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the first interlayer insulating film is a silicon rich oxide film. 제2항에 있어서, 상기 실리콘 리치 산화막은 300 내지 350℃의 온도에서 PECVD 방식으로 형성되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 2, wherein the silicon rich oxide film is formed by PECVD at a temperature of 300 to 350 ° C. 4. 제1항에 있어서, 상기 경화 공정은 300 내지 350℃의 온도에서 70 내지 100초동안 실시되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the curing process is performed at a temperature of 300 to 350 ° C. for 70 to 100 seconds. 제1항에 있어서, 상기 소성 공정은 400 내지 420℃의 온도 및 질소(N2) 가스 분위기 하에서 50 내지 70분동안 실시되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the firing step is performed at a temperature of 400 to 420 ° C. and a nitrogen (N 2 ) gas atmosphere for 50 to 70 minutes. 제1항에 있어서, 상기 열처리는 150 내지 200mTorr의 압력 및 350 내지 400℃의 온도 조건에서 50 내지 70분동안 실시되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the heat treatment is performed at a pressure of 150 to 200 mTorr and a temperature of 350 to 400 ° C. for 50 to 70 minutes. 제1항에 있어서, 상기 제2금속층간 절연막은 TEOS막인 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 1, wherein the second interlayer insulating film is a TEOS film. 제7항에 있어서, 상기 TEOS막은 350 내지 450℃의 온도에서 PECVD 방식으로 형성되는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성 방법.The method of claim 7, wherein the TEOS film is formed by PECVD at a temperature of 350 to 450 ° C. 9.
KR1019960022813A 1996-06-22 1996-06-22 Method for forming interlayer insulating film of semiconductor device KR980006122A (en)

Priority Applications (1)

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KR1019960022813A KR980006122A (en) 1996-06-22 1996-06-22 Method for forming interlayer insulating film of semiconductor device

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KR1019960022813A KR980006122A (en) 1996-06-22 1996-06-22 Method for forming interlayer insulating film of semiconductor device

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KR980006122A true KR980006122A (en) 1998-03-30

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