KR19980038456A - Bit line formation method of semiconductor device - Google Patents
Bit line formation method of semiconductor device Download PDFInfo
- Publication number
- KR19980038456A KR19980038456A KR1019960057360A KR19960057360A KR19980038456A KR 19980038456 A KR19980038456 A KR 19980038456A KR 1019960057360 A KR1019960057360 A KR 1019960057360A KR 19960057360 A KR19960057360 A KR 19960057360A KR 19980038456 A KR19980038456 A KR 19980038456A
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- KR
- South Korea
- Prior art keywords
- forming
- bit line
- tungsten silicide
- polysilicon layer
- layer
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
본 발명은 반도체 소자의 비트라인 형성방법에 관한 것으로, 소정의 제조공정을 거쳐 콘택홀이 형성된 실리콘 기판의 전체 상부면에 폴리실리콘층을 형성하고, 이 폴리실리콘층 상에 인시튜로 텅스텐 실리사이드층을 형성한 후 열처리 공정을 실시함으로써 폴리실리콘층 및 텅스텐 실리사이드층 간의 저항을 감소시킬 수 있고, 텅스텐 실리사이드층의 들뜸현상을 방지하며, 또한 공정의 단순화로 인하여 소자의 수율을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, wherein a polysilicon layer is formed on the entire upper surface of a silicon substrate on which contact holes are formed through a predetermined manufacturing process, and a tungsten silicide layer is in situ on the polysilicon layer. After forming a heat treatment process, the resistance between the polysilicon layer and the tungsten silicide layer can be reduced, the lifting of the tungsten silicide layer can be prevented, and the yield of the device can be improved due to the simplification of the process. have.
Description
본 발명은 반도체 소자의 비트라인 형성방법에 관한 것으로 특히, 폴리 실리콘층 및 텅스텐 실리사이드층을 인시튜로 형성할 수 있는 비트라인 형성방법에 관한 것이다.The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a method for forming a bit line in which a polysilicon layer and a tungsten silicide layer can be formed in situ.
일반적으로, 반도체 소자의 제조공정에서 게이트 전극(워드라인) 또는 비트라인 등을 형성할 때 폴리실리콘을 주로 사용하였다. 그러나, 최근 소자가 고집적화 되고 소자의 빠른 동작속도가 요구되고 있기 때문에 반도체 소자의 제조공정에서 비교적 높은 저항을 갖고있는 폴리실리콘의 사용에는 한계가 있다. 따라서, 폴리실리콘의 높은 저항을 개선하기 위한 방안으로 하부층을 폴리실리콘으로 형성하고, 상부층을 열적 안정성과 낮은 저항성의 특성을 갖는 텅스텐 실리사이드로 형성한 폴리사이드 구조가 반도체 소자의 제조공정에 많이 사용되고 있다. 종래에는 이러한 폴리사이드 구조를 갖는 위드라인 및 비트라인을 형성하기 위하여 소정의 제조공정을 거쳐 접합영역이 노출되도록 콘택홀이 형성된 실리콘 기판의 전체 상부면에 폴리실리콘층을 저압 화학 기상 증착(LPCVD) 방법으로 형성한다. 이렇게 형성된 폴리실리콘층의 표면에 세정공정을 실시한 후 그 위에 텅스텐 실리사이드층을 형성한다. 이와 같이 종래 방법에 의해 형성되는 폴리사이드 구조는 폴리실리콘층 형성 후 세정공정을 실시함으로써 공정이 복잡해 지며 텅스텐 실리사이드층은 후속 열처리 공정시 들뜸(Peeling) 현상이 빈번이 발생되어 소자의 수율을 저하시키는 문제가 있다.In general, polysilicon is mainly used to form a gate electrode (word line) or a bit line in a semiconductor device manufacturing process. However, due to the recent high integration of devices and the rapid operation speed of devices, there is a limit to the use of polysilicon having a relatively high resistance in the manufacturing process of semiconductor devices. Therefore, a polyside structure in which a lower layer is formed of polysilicon and an upper layer is formed of tungsten silicide having thermal stability and low resistance as a method for improving the high resistance of polysilicon is widely used in the manufacturing process of semiconductor devices. . Conventionally, low pressure chemical vapor deposition (LPCVD) of a polysilicon layer is formed on the entire upper surface of a silicon substrate in which contact holes are formed through a predetermined manufacturing process to form a weed line and a bit line having such a polyside structure. To form. After the cleaning process is performed on the surface of the polysilicon layer thus formed, a tungsten silicide layer is formed thereon. As described above, the polyside structure formed by the conventional method is complicated by the cleaning process after the polysilicon layer is formed, and the tungsten silicide layer frequently causes the phenomenon of peeling during the subsequent heat treatment process to decrease the yield of the device. there is a problem.
따라서 본 발명은 소정의 공정을 거쳐 접합영역이 노출되도록 콘택홀이 형성된 실리콘 기판의 전체 상부면에 인시튜(In Situ)로 폴리실리콘층 및 텅스텐 실리사이드층을 순차적으로 형성한 후 열처리 공정을 실시하여 폴리사이드 구조를 갖는 반도체 소자의 비트라인 형성방법을 제공하는 것을 그 목적으로 한다.Therefore, the present invention sequentially forms a polysilicon layer and a tungsten silicide layer in situ on the entire upper surface of the silicon substrate where the contact holes are formed to expose the junction region through a predetermined process, and then performs a heat treatment process. It is an object of the present invention to provide a method for forming a bit line of a semiconductor device having a polyside structure.
상술한 목적을 실현하기 위한 본 발명에 따른 비트라인 형성방법은 소정의 제조공정을 거쳐 게이트 전극 및 접합영역이 형성된 실리콘 기판의 전체 상부면에 절연막을 형성하는 단계와, 접합영역이 노출되도록 절연막을 식각하여 콘택홀을 형성한 후 실리콘 기판의 전체 상부면에 폴리실리콘층을 형성하는 단계와, 폴리실리콘층 상에 인시튜로 텅스텐 실리사이드층을 형성한 후 열처리 공정을 실시하는 단계로 이루어진다.The bit line forming method according to the present invention for realizing the above object comprises the steps of forming an insulating film on the entire upper surface of the silicon substrate on which the gate electrode and the junction region are formed through a predetermined manufacturing process, the insulating film is exposed so that the junction region is exposed; After forming the contact hole by etching, forming a polysilicon layer on the entire upper surface of the silicon substrate, and forming a tungsten silicide layer in-situ on the polysilicon layer and then performing a heat treatment process.
도 1a 내지 1d는 본 발명에 따른 반도체 소자의 비트라인 형성방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming a bit line of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 게이트 전극1 silicon substrate 2 gate electrode
3 : 접합영역 4 : 절연막3: junction region 4: insulating film
5 : 폴리실리콘층 6 : 텅스텐 실리사이드층5: polysilicon layer 6: tungsten silicide layer
10 : 콘택홀10: contact hole
이하, 본 발명에 따른 비트라인 형성방법을 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a bit line forming method according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1d는 비트라인 형성방법을 설명하기 위한 소자의 단면도로서, 도 1a는 소정의 제조공정을 거쳐 게이트 전극(2) 및 접합영역(3)이 형성된 실리콘 기판(1)의 전체 상부면에 BPSG로 이루는 절연막(4)을 형성한 상태를 도시한다.1A to 1D are cross-sectional views of a device for explaining a bit line forming method, and FIG. 1A is a view showing an entire upper surface of a silicon substrate 1 on which a gate electrode 2 and a junction region 3 are formed through a predetermined manufacturing process. The state where the insulating film 4 which consists of BPSG is formed is shown.
도 1b는 접합영역(3)이 노출되도록 절연막(4)을 식각하여 콘택홀(10)을 형성한 상태를 도시하며, 도 1c는 실리콘 기판(1)의 전체 상부면에 폴리실리콘층(5)을 형성한 상태를 도시한다. 폴리실리콘층(5)은 SiH4및 SiCl2H2를 소스가스로 이용하여 2000 내지 3000Å의 두께로 형성된다.FIG. 1B illustrates a state in which the contact hole 10 is formed by etching the insulating film 4 so that the junction region 3 is exposed, and FIG. 1C illustrates the polysilicon layer 5 on the entire upper surface of the silicon substrate 1. The state which formed the is shown. The polysilicon layer 5 is formed to a thickness of 2000 to 3000 kPa using SiH 4 and SiCl 2 H 2 as source gases.
도 1d는 폴리실리콘층(5) 상에 인시튜로 텅스텐 실리사이드층(6)을 형성한 후 열처리 공정을 실시한 상태를 도시한다. 텅스텐 실리사이드층(6)은 WF6및 SiH4를 소스가스로 이용하여 1500 내지 2500Å의 두께로 형성된다. 그리고, 열처리 공정은 390 내지 430℃의 온도 조건에서 20 내지 40분간 실시된다. 이렇게하여 폴리실리콘층(5) 및 텅스텐 실리사이드층(6)이 적층됨으로써 폴리사이드 구조를 갖는 비트라인이 형성된다.FIG. 1D shows a state in which the tungsten silicide layer 6 is formed in situ on the polysilicon layer 5 and then subjected to a heat treatment process. The tungsten silicide layer 6 is formed to a thickness of 1500 to 2500 kW using WF 6 and SiH 4 as source gas. Then, the heat treatment step is carried out for 20 to 40 minutes at a temperature condition of 390 to 430 ℃. In this way, the polysilicon layer 5 and the tungsten silicide layer 6 are laminated to form a bit line having a polyside structure.
본 실시예에서는 비트라인 형성방법에 대하여 설명하였으나 본 발명은 이것에 한정되는 것은 아니다. 즉, 게이트 전극을 인출하기 위한 워드라인 형성에 대해서 적용할 수 있음은 물론이다.Although the bit line forming method has been described in the present embodiment, the present invention is not limited thereto. That is, of course, it can be applied to the word line formation for drawing out the gate electrode.
상술한 바와 같이 본 발명에 의하면 소정의 공정을 거쳐 접합영역이 노출되도록 콘택홀이 형성된 실리콘 기판의 전체 상부면에 인시튜로 폴리실리콘층 및 텅스텐 실리사이드층을 순차적으로 형성한 후 열처리 공정을 실시하여 폴리실리콘층 및 텅스텐 실리사이드층 간의 저항을 감소시킬 수 있고, 텅스텐 실리사이드층의 들뜸현상을 방지하며, 또한 공정의 단순화로 인하여 소자의 수율을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, a polysilicon layer and a tungsten silicide layer are sequentially formed in situ on the entire upper surface of the silicon substrate on which the contact holes are formed through a predetermined process, and then subjected to a heat treatment process. The resistance between the polysilicon layer and the tungsten silicide layer may be reduced, the lifting of the tungsten silicide layer may be prevented, and the yield of the device may be improved due to the simplification of the process.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960057360A KR19980038456A (en) | 1996-11-26 | 1996-11-26 | Bit line formation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960057360A KR19980038456A (en) | 1996-11-26 | 1996-11-26 | Bit line formation method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19980038456A true KR19980038456A (en) | 1998-08-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960057360A KR19980038456A (en) | 1996-11-26 | 1996-11-26 | Bit line formation method of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100640566B1 (en) * | 2000-01-31 | 2006-10-31 | 삼성전자주식회사 | A semiconductor device comprising an double pad layer and method for manufacturing the same |
-
1996
- 1996-11-26 KR KR1019960057360A patent/KR19980038456A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100640566B1 (en) * | 2000-01-31 | 2006-10-31 | 삼성전자주식회사 | A semiconductor device comprising an double pad layer and method for manufacturing the same |
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