KR940001378A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940001378A
KR940001378A KR1019920009622A KR920009622A KR940001378A KR 940001378 A KR940001378 A KR 940001378A KR 1019920009622 A KR1019920009622 A KR 1019920009622A KR 920009622 A KR920009622 A KR 920009622A KR 940001378 A KR940001378 A KR 940001378A
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KR
South Korea
Prior art keywords
bpsg
film
semiconductor device
manufacturing
bpsg film
Prior art date
Application number
KR1019920009622A
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Korean (ko)
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KR100269272B1 (en
Inventor
임영진
강긍원
이주범
박승갑
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920009622A priority Critical patent/KR100269272B1/en
Publication of KR940001378A publication Critical patent/KR940001378A/en
Application granted granted Critical
Publication of KR100269272B1 publication Critical patent/KR100269272B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 다층배선 구조에서 층간절연막으로 BPSG막을 사용하는 반도체장치의 제조방법에 있어서, 상기 BPSG막에 콘택트 홀 형성을 위한 제1마스크패턴의 형성전에, 상기 BPSG막을 표면처리하는 공정을 구비하는 것을 특징으로 한다. 따라서 본 발명에 의한 충간절연막의 형성방법은, 종래 층간절연막으로 사용되는 고농도의 BPSG막에 발생하던 스웰링현상을 상기 BPSG막의 표면처리를 통해 제거할 수 있게 되어, 저온 BPSG 평탄화를 위한 고농도의 BPSG막을 적용할 수 있게 되었다BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device using a BPSG film as an interlayer insulating film in a multi-layer wiring structure, wherein the BPSG is formed before formation of a first mask pattern for forming a contact hole in the BPSG film. And a step of surface treating the film. Therefore, in the method of forming the interlayer insulating film according to the present invention, the swelling phenomenon generated in the high concentration BPSG film used as the conventional interlayer insulating film can be removed through the surface treatment of the BPSG film, and the high concentration BPSG for planarization of low temperature BPSG Act can be applied

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명에 의한 층간절연막의 형성방법을 나타낸 공정순서도.2A to 2F are process flow charts showing a method for forming an interlayer insulating film according to the present invention.

Claims (4)

다층배선구조에서 층간절연막으로 BPSG막을 사용하는 반도체장치 제조방법에 있어서, 상기 BPSG막에 콘택트 홀 형성을 위한 제 1마스크패턴의 형성전에, 상기 BPSG막을 표면처리하는 공정을 구비하는 것을 특징으로 하는 반도체장치의 제조방법,A semiconductor device manufacturing method using a BPSG film as an interlayer insulating film in a multi-layer wiring structure, comprising the step of surface treating the BPSG film before forming the first mask pattern for forming contact holes in the BPSG film. Manufacturing method of the device, 제1항에 있어서, 상기 제1마스크패턴은 포토레지스트 패턴인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the first mask pattern is a photoresist pattern. 제1항에 있어서, 상기 BPSG막의 표면처리는 N2O플라즈마처리. 후은 02플라츠마처리. 혹은 아르곤 에치백 공정을 사용하는 것을 특징으로 하는 반도체장치의 제조방법.The surface treatment of the BPSG film is N 2 O plasma treatment. After the 0 2 plasma treatment. Or an argon etch back process. 제3항에 있어서, 상기 아르곤 에치 백 공정은 상기 BPSG막을 표면으로 부터 300A∼500A정도 식각함으로써 이루어지는 것을 특징으로 하는 반도체장치의 제로방법.4. The zero method of a semiconductor device according to claim 3, wherein said argon etch back process is performed by etching said BPSG film from about 300A to 500A from a surface thereof. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920009622A 1992-06-03 1992-06-03 Method for manufacturing semiconductor device KR100269272B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920009622A KR100269272B1 (en) 1992-06-03 1992-06-03 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920009622A KR100269272B1 (en) 1992-06-03 1992-06-03 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR940001378A true KR940001378A (en) 1994-01-11
KR100269272B1 KR100269272B1 (en) 2000-10-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920009622A KR100269272B1 (en) 1992-06-03 1992-06-03 Method for manufacturing semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100372640B1 (en) * 2000-06-28 2003-02-17 주식회사 하이닉스반도체 Method for forming contact plug using selective epitaxial growth
KR101105603B1 (en) * 2011-09-05 2012-01-19 (주)유바이오시스 Collagen solution manufacturing method using a saline precipitation enrichment method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2804543B2 (en) * 1989-10-23 1998-09-30 宮崎沖電気株式会社 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100372640B1 (en) * 2000-06-28 2003-02-17 주식회사 하이닉스반도체 Method for forming contact plug using selective epitaxial growth
KR101105603B1 (en) * 2011-09-05 2012-01-19 (주)유바이오시스 Collagen solution manufacturing method using a saline precipitation enrichment method

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Publication number Publication date
KR100269272B1 (en) 2000-10-16

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