KR930024098A - Wiring Formation Method of Semiconductor Device - Google Patents

Wiring Formation Method of Semiconductor Device Download PDF

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Publication number
KR930024098A
KR930024098A KR1019920008260A KR920008260A KR930024098A KR 930024098 A KR930024098 A KR 930024098A KR 1019920008260 A KR1019920008260 A KR 1019920008260A KR 920008260 A KR920008260 A KR 920008260A KR 930024098 A KR930024098 A KR 930024098A
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KR
South Korea
Prior art keywords
sog
etched
wiring
semiconductor device
bpsg
Prior art date
Application number
KR1019920008260A
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Korean (ko)
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KR950010043B1 (en
Inventor
송승룡
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019920008260A priority Critical patent/KR950010043B1/en
Publication of KR930024098A publication Critical patent/KR930024098A/en
Application granted granted Critical
Publication of KR950010043B1 publication Critical patent/KR950010043B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 BPSG ILD 공정 이후 SOG 절연막을 먼저 도포, 열처리하여 배선 패턴을 식각하는 역(Reverse)공정으로 미세 패턴을 단일 리소그라피(Lithography)공정으로 쉽게 이룰 수 있게 하고, 텅스텐 라인을 식각 공정으로 하지 않고 에치백 공정으로 형성함으로써 미세 패턴을 형성할 수 있도록 한 것이다. 반도체소자의 여러가지요소들(20)을 형성한 다음 BPSG를 증착하고 리플로우(Reflow)시킨 다음 SOG를 5000Å이상 도포한 후, 500℃이상의 온도에서 열처리한후, 리소그라피 공정을 진행하여 배선 패턴이 이루어질 부분의 SOG를 에치한 다음에, 식가된 SOG 패턴 위에 텅스탠(W)을 증착하고, 에치백하여 배선을 형성한다.The present invention is a reverse process of etching the wiring pattern by first applying and heat treating the SOG insulating film after the BPSG ILD process, so that the micropattern can be easily formed by a single lithography process, and the tungsten line is not etched. By forming by the etch back process, it is possible to form a fine pattern. After the various elements 20 of the semiconductor device are formed, BPSG is deposited, reflowed, SOG is applied at 5000Å or more, heat treated at a temperature of 500 ° C. or more, and then a lithography process is performed to form a wiring pattern. After etching the part SOG, the tungsten W is deposited on the etched SOG pattern and etched back to form wiring.

Description

반도체소자의 배선 형성방법Wiring Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 방법을 설명하기 위한 개략 단면도.2 is a schematic cross-sectional view for explaining the method of the present invention.

Claims (3)

반도체소자의 여러 요소들을 형성한 후 배선을 형성하는 방법에 있어서,(1)웨이퍼상에 BPSG를 데포지션하고 리플로우시키는 단계; (2)SOG를 도포한 후, 500℃이상의 온도에서 열처리하는 단계; (3)리소그라피 공정을 실시하여 배선이 될 부분의 SOG를 식각하고, 콘택홀을 형성하는 단계; (4)식각된 SOG패턴 및 콘택홀 위에 텅스텐을 증착하고 에치백하여 텅스텐 배선을 형성하는 단계를 포함하여 이루어지는 반도체소자의 배선 형성방법.A method of forming wiring after forming various elements of a semiconductor device, the method comprising: (1) depositing and reflowing a BPSG on a wafer; (2) after applying the SOG, heat treatment at a temperature of 500 ℃ or more; (3) performing a lithography process to etch the SOG in the portion to be wired and form contact holes; And (4) depositing tungsten on the etched SOG pattern and contact hole and etching back to form tungsten wiring. 제1항에 있어서, 제(2)단계에서 SOG를 5000Å 이상 도포하는 것이 특징인 반도체소자의 배선 형성방법.The method for forming a wiring of a semiconductor device according to claim 1, wherein in step (2), SOG is applied at 5000 kPa or more. 제1항에 있어서, 제(3)단계에서 처음에는 얕은 부분의 SOG를 식각하고, 다음에는 깊은 부분의 SOG까지를 시각하기 위하여 SOG가 BPSG보다 빨리 에치되도록 하여 콘택부위까지 식각하는 것이 특징인 반도체소자의 배선 형성방법.2. The semiconductor of claim 1, wherein in step (3), the SOG in the shallow portion is first etched, and then the SOG is etched faster than the BPSG to etch the contact portion so as to visualize the SOG in the deep portion. Method for forming wiring of the device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920008260A 1992-05-15 1992-05-15 Metalizing method of semiconductor device KR950010043B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920008260A KR950010043B1 (en) 1992-05-15 1992-05-15 Metalizing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920008260A KR950010043B1 (en) 1992-05-15 1992-05-15 Metalizing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR930024098A true KR930024098A (en) 1993-12-21
KR950010043B1 KR950010043B1 (en) 1995-09-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920008260A KR950010043B1 (en) 1992-05-15 1992-05-15 Metalizing method of semiconductor device

Country Status (1)

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KR (1) KR950010043B1 (en)

Also Published As

Publication number Publication date
KR950010043B1 (en) 1995-09-06

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