KR950010043B1 - Metalizing method of semiconductor device - Google Patents
Metalizing method of semiconductor device Download PDFInfo
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- KR950010043B1 KR950010043B1 KR1019920008260A KR920008260A KR950010043B1 KR 950010043 B1 KR950010043 B1 KR 950010043B1 KR 1019920008260 A KR1019920008260 A KR 1019920008260A KR 920008260 A KR920008260 A KR 920008260A KR 950010043 B1 KR950010043 B1 KR 950010043B1
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- bpsg
- sog
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
제1도는 종래기술을 설명하기 위한 개략 단면도.1 is a schematic cross-sectional view for explaining the prior art.
제2도는 발명의 방법을 설명하기 위한 개략 단면도.2 is a schematic cross-sectional view for explaining the method of the invention.
본 발명은 SOG(spin on glass)와 텅스텐(W) 공정을 이용하여 반도체소자의 배선을 형성하는 방법에 관한 것이다. 특히, BPSG(born phosphoilica glass)형성 공정에서 발생하는 단차를 5000Å미만으로 줄일 수 있으며, 텅스텐을 사진 식각 공정으로 패터닝(patterning)하지 아니하고 에치백(etch-back)공정으로 패터닝하여 0.4㎛이하로 미세 패턴 형성을 가능하게 하는 반도체소자의 배선형성방법에 관한 것이다.The present invention relates to a method for forming a wiring of a semiconductor device using a spin on glass (SOG) and tungsten (W) process. In particular, it is possible to reduce the step difference generated in the process of forming BPSG (born phosphoilica glass) to less than 5000Å, and pattern the fine tungsten to 0.4㎛ or less by patterning the tungsten by an etch-back process without patterning by photolithography. The present invention relates to a wiring forming method of a semiconductor device that enables pattern formation.
제1도는 종래 방법을 설명하기 위한 개략 단면도1 is a schematic cross-sectional view for explaining the conventional method.
종래의 방법은, 먼저 제1a도와 같이, 반도체 기판에 필요한 회로 요소들(편의상 상세한 도시는 생략한다.)을 형성시킨 다음 배선층과 하부 도전층과 전기적 절연을 위하여 BPSG를 증착하고 리플로우(Reflow)시킨다. 캐패시터(capacitor)등의 회로요소들이 형성된 부분은 높고 기타부분은 낮아서 BPSG를 도포하여도 이 단차는 없어지지 아니한다.The conventional method first forms the circuit elements necessary for the semiconductor substrate (not shown in detail for convenience), as shown in FIG. 1A, and then deposits and reflows BPSG for electrical insulation with the wiring layer and the lower conductive layer. Let's do it. The part where the circuit elements such as the capacitor are formed is high and the other part is low so that the step is not lost even when BPSG is applied.
다음에 제1b도와 같이, 배선용으로 알미늄(A1)을 증착하고 사진 식각공정으로 알미늄을 배선으로 페터닝 한다.Next, as shown in FIG. 1B, aluminum (A1) is deposited for wiring, and aluminum is patterned by wiring by a photolithography process.
그후, 제1c도와 같이, 알미늄패턴위에 층간절연막으로 SOG또는 TEOS(tetra-ethyl-orthosilicate)등을 데포지션(deposition)한다.Thereafter, as shown in FIG. 1C, SOG or tetra-ethyl-orthosilicate (TEOS) or the like is deposited on the aluminum pattern as an interlayer insulating film.
마지막으로, 제1d도와 같이, 층간절염막 위에 다시 배선용 메탈(metal)을 데포지션하고 페터닝하여 제2층 배선을 제작 완료한다.Finally, as shown in FIG. 1D, the wiring metal is again deposited and patterned on the interlayer dye film to complete the fabrication of the second layer wiring.
이상 설명한 바와 같은 종래의 배선 형성방법은 반도체소자의 캐패시터 형성후에 발생되는 셀 영역과 페리 영역과의 1.0㎛가 넘는 단차로 인하여 메탈의 미세패턴 형성시 포카스(focus)문제로 매우 어렵게 되고, 미세한 텅스텐 배선에는 적용하기가 어렵다.As described above, the conventional wiring forming method becomes very difficult due to the focus problem when forming a fine pattern of metal due to the difference of more than 1.0 μm between the cell region and the ferry region generated after the capacitor formation of the semiconductor device. It is difficult to apply to wiring.
본 발명에서 BPSG, 층간절염막(ILD; Inter Layer dielectric)공정 이후 SOG절연막을 먼저 도포, 열처리하여 배선 패턴을 식각하는 역(Reverse)공정으로 미세패턴을 단일 리소그라피(Lithography)공정으로 쉽게 이룰 수 있게하고, 텅스텐라인(W-line)을 식각공정으로 하지 않고 에치백 공정으로 형성함으로써 미세 패턴을 형성할 수 있도록 한 것이다.In the present invention, after the BPSG and inter layer dielectric (ILD) processes, the SOG insulating film is first applied and heat treated to reverse the etching of the wiring pattern so that the micropattern can be easily formed in a single lithography process. In addition, a fine pattern may be formed by forming a tungsten line (W-line) by an etch back process instead of an etching process.
즉, 본 발명에 의한 반도체소자의 배선 형성방법에서는 반도체소자의 여러 요소들을 형성하여 단차가 형성된 웨이퍼상에 BPSG를 형성하는 단계와, BPSG위에 SOG을 형성하는 단계와, 배선패턴영역 및 콘택부위의 BPSG와 SOG을 식각하는 단계와, SOG와 BPSG가 식각된 배선 패턴영역 및 콘텍부위에 텅스텐 배선을 형성하는 단계를 포함하여 이루어진다.That is, in the method for forming a wiring of a semiconductor device according to the present invention, forming BPSG on a stepped wafer by forming various elements of the semiconductor device, forming SOG on the BPSG, and forming a wiring pattern region and a contact portion Etching the BPSG and the SOG; and forming tungsten wiring in the wiring pattern region and the contact portion where the SOG and the BPSG are etched.
제2도를 참조하면서 본 발명의 방법을 설명한다.The method of the present invention will be described with reference to FIG.
먼저, 제2a도와 같이, 반도체소자의 여러가지 요소들을 형성한 다음 BPSG를 증착하고 리플로우(Reflow)시킨다.First, as shown in FIG. 2A, various elements of the semiconductor device are formed, and then BPSG is deposited and reflowed.
다음에, 제2b도와 같이 SOG를 5000Å이상 도포한 후, 500℃이상의 온도에서 열처리한다.Next, SOG is applied at 5000 Pa or more as shown in FIG.
그후, 제2c도와 같이 리소그라피 공정을 진행하여 배선 패턴이 이루어질 부분의 BPSG와 SOG를 식각하며, 이때 콘텍홀(contact hole)도 같이 형성된다.Thereafter, as shown in FIG. 2C, a lithography process is performed to etch BPSG and SOG in a portion where the wiring pattern is to be formed, and a contact hole is also formed.
그리고 BPSG와 SOG의 에칭공정은 처음에는 얕은 부분의 SOG를 도면에서 “A”로 표시된 부분까지 식각하고, 다음에는 깊은 부분의 SOG까지의 “B”로 표시된 곳까지 식각하기 위하여 SOG가 BPSG보다 빨리 에치되도록 하여 (대략 2배정도 빠르게) BPSG위의 SOG를 식각하며, 이후에는 반대로 BPSG가 SOG보다 빨리 에치되도록 하여 (대략 2배정도 빠르게) “C”로 표시된 콘텍부위까지 식각한다.In the etching process of BPSG and SOG, SOG is faster than BPSG in order to etch the shallow SOG to the point marked “A” in the drawing and then to the point marked “B” to the deep SOG. Etching the SOG on the BPSG (approximately twice as fast) and then etching the SOG over the BPSG on the contrary, then etching the contact area marked "C" (approximately twice as fast).
즉, BPSG와 SOG의 에칭가스(etching gas; etchant)는 CHF3, CF4, Ar등을 사용하고, 이중에서 CHF3,CF4의 비율을 조절하여 BPSG와 SOG의 식각비를 조절하며, SOG의 식각속도는 SOG에 포함되어 있는 유기적 결합(organic bond)과 CHF3의 양에 따라 변하므로, BPSG위에 형성된 SOG의 유기적 결합의 양이 일정하다고 가정하면 CHF3의 양에 따라 SOG의 식각속도가 변하게 되며, 또한 BPSG는 CF4의 양에 따라 식각속도가 다르게 된다.That is, the etching gas (etchant) of BPSG and SOG is used as CHF 3 , CF 4 , Ar, etc. Among them, the ratio of CHF 3, CF 4 is controlled to control the etching ratio of BPSG and SOG, and SOG The etching rate of is changed according to the amount of organic bond and CHF 3 contained in SOG. Therefore, assuming that the amount of organic bond of SOG formed on BPSG is constant, the etching rate of SOG depends on the amount of CHF 3 . In addition, the BPSG has different etching rates depending on the amount of CF 4 .
따라서 SOG를 “A”로 표시된 부분까지 식각한 후에, CF4의 양보다 CHF3의 양을 증가시켜서 에칭가스를 구성하고, “B”로 표시된 부분까지 식각하면 BPSG보다 SOG를 더 빠른 속도로 식각할 수 있고, “C”로 표시된 부분까지는 CHF3보다 CH4의 양을 증가시켜 에칭가스를 구성하면 SOG보다 BPSG가 더 빠른 속도로 식각된다.Therefore, after etching SOG to the part marked “A”, the etching gas is formed by increasing the amount of CHF 3 rather than the amount of CF 4 , and etching to the part marked “B” etches the SOG faster than BPSG. If the etching gas is formed by increasing the amount of CH 4 to CHF 3 , the BPSG is etched faster than SOG.
다음에, 제 2d도와 같이 식각된 SOG패턴과 콘택홀 위에 텅스텐(W)을 증착하고, 에치백하여 배선을 형성한다.Next, tungsten (W) is deposited on the etched SOG pattern and the contact hole as shown in FIG. 2d and etched back to form a wiring.
그리고 제 2e도와 같이, 층간절연막(ILD,IMD(Inter Metal dielectric))등을 데포지션한 뒤 2층 배선용 메탈을 데포지션하고 패터닝하여 2층 배선을 형성한다.As shown in FIG. 2E, the interlayer dielectric film (ILD, IMD (Inter Metal dielectric)) and the like are deposited, and the metal for 2-layer wiring is deposited and patterned to form a 2-layer wiring.
이렇게 함으로써, BPSG공정 후 높은 평탄도를 이룰 수가 있게 된다.In this way, high flatness can be achieved after the BPSG process.
그리고, SOG도표하고 열처리하여 BPSG공정에서 발생하는 단차를 5000Å미만으로 줄일 수 있으며, 텅스텐을 사진 식각 공정으로 패터닝하지 아니하고 에치백 공정으로 패터닝하여 0.4μm이하로 미세 패턴 형성을 가능하게 한다.In addition, the SOG diagram and heat treatment can reduce the step difference generated in the BPSG process to less than 5000 ,, and pattern the tungsten by the etchback process without patterning the photoetch process to enable the formation of a fine pattern below 0.4μm.
즉, 본 발명에 의한 반도체소자의 배선 형성방법에서는 높는 평탄도로 인하여 미세한 패턴을 정의하기 위한 포토공정에서 단차의 영향없이 마스크에 있는 패턴을 기판(웨이퍼)상에 전사시킬 수 있으며, 반도체소자의 페리 부분, 센스 앰프, 디코더 등에서 1층 배선의 디멘션을 Y방향으로 단차만큼 증대하여 배선 저항을 감소할 수 있게 된다.That is, in the wiring forming method of the semiconductor device according to the present invention, the pattern in the mask can be transferred onto the substrate (wafer) without affecting the step in the photo process for defining the fine pattern due to the high flatness. In the part, sense amplifier, decoder, etc., the dimension of the one-layer wiring can be increased by a step in the Y direction to reduce the wiring resistance.
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KR1019920008260A KR950010043B1 (en) | 1992-05-15 | 1992-05-15 | Metalizing method of semiconductor device |
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KR1019920008260A KR950010043B1 (en) | 1992-05-15 | 1992-05-15 | Metalizing method of semiconductor device |
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KR950010043B1 true KR950010043B1 (en) | 1995-09-06 |
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