KR970003494A

KR970003494A - Method of forming contact hole in manufacturing semiconductor device

Info

Publication number: KR970003494A
Application number: KR1019950017567A
Authority: KR
Inventors: 최양규
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-06-26
Filing date: 1995-06-26
Publication date: 1997-01-28

Abstract

본 발명은 반도체 소자 제조시 예정된 패턴이 형성된 기판(1)의 전체 구조상에 평탄화 절연층(5)을 형성하는 단계와, 상기 평탄화 절연층 상에 콘택홀 형성을 위한 감광층(6) 패턴을 형성하는 단계를 포함하는 콘택홀 형성 방법에 있어서, 노출된 상기 평탄화 절연층을 일정 깊이 비등방 식각하는 제1단계; 상기 감광층 패턴을 등방식각하여 수직방향 및 수평방향으로 일정 두께 제거하는 제2단계; 및 남아 있는 상기 감광층 패턴을 이용하여 상기 평탄화 절연층을 비등방 식각하여 예정된 전도층(3,4)을 노출시킨 후 상기 감광층 패턴을 제거하는 제3단계를 포함하는 것을 특징으로 하는 콘택홀 형성 방법에 관한 것으로, 수평방향의 과도한 식각을 방지할 수 있으며, 이에 따라 감광층의 붕괴 위험을 감소시키고, 콘택홀간의 최소 이격 간격을 감소시킬 수 있어 소자의 집적도를 향상시킬 수 있으며, 또한, 식각장비로 비등방식각을 위한 식각장비 하나만 사용해도 되기 때문에 제조 단가를 감소시킬 수 있도록 한 것이다.According to the present invention, a planarization insulating layer 5 is formed on an entire structure of a substrate 1 on which a predetermined pattern is formed in manufacturing a semiconductor device, and a photosensitive layer 6 pattern for forming a contact hole is formed on the planarizing insulating layer. A contact hole forming method comprising: a first step of anisotropically etching an exposed depth of the planarization insulating layer; A second step of removing the thickness of the photosensitive layer pattern in a vertical direction and a horizontal direction by an isometric angle; And forming a contact hole by anisotropically etching the planarization insulating layer using the remaining photosensitive layer pattern to expose the predetermined conductive layers 3 and 4 and then removing the photosensitive layer pattern. Method, which can prevent excessive etching in the horizontal direction, thereby reducing the risk of collapse of the photosensitive layer, and reducing the minimum separation distance between contact holes, thereby improving the integration of the device, and also etching. It is possible to reduce the manufacturing cost because only one etching equipment for boiling corrosion angle can be used as the equipment.

Description

Method of forming contact hole in manufacturing semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1E도는 본 발명에 따른 콘택홀의 형성 과정도.1E is a process diagram of forming a contact hole according to the present invention.

Claims

A method of forming a contact hole, comprising: forming a planarization insulating layer on an entire structure of a substrate on which a predetermined pattern is formed during fabrication of a semiconductor device; and forming a photosensitive layer pattern for forming a contact hole on the planarization insulating layer. A first step of anisotropically etching the exposed planarization insulating layer; A second step of removing the thickness of the photosensitive layer pattern in a vertical direction and a horizontal direction by an isometric angle; And a third step of exposing a predetermined conductive layer by boiling the planarization insulating layer using the remaining photosensitive layer pattern, and then removing the photosensitive layer pattern.

The method of claim 1, wherein the second step is performed in the same chamber used in the first step.

The method of claim 2, wherein the second step is performed using either oxygen (O ₂ ) plasma or argon (Ar) plasma.

The contact hole formation according to any one of claims 1 to 3, wherein the second step is performed such that the etching rate of the corner portion of the photosensitive layer pattern is increased so that the photosensitive layer pattern after etching has a predetermined slope. Way.

The method of claim 4, wherein the horizontal etching thickness (A) of the photosensitive layer pattern is formed as large as possible to reduce the step ratio within the limit to ensure a certain amount of space between adjacent conductors. Way.

※ Note: The disclosure is based on the initial application.