KR101077021B1 - Method of forming a metal line in a semiconductor devices - Google Patents
Method of forming a metal line in a semiconductor devices Download PDFInfo
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- KR101077021B1 KR101077021B1 KR1020030098839A KR20030098839A KR101077021B1 KR 101077021 B1 KR101077021 B1 KR 101077021B1 KR 1020030098839 A KR1020030098839 A KR 1020030098839A KR 20030098839 A KR20030098839 A KR 20030098839A KR 101077021 B1 KR101077021 B1 KR 101077021B1
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 75
- 238000005530 etching Methods 0.000 claims abstract description 66
- 239000010410 layer Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 229920002313 fluoropolymer Polymers 0.000 claims abstract description 11
- 238000001465 metallisation Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 239000007769 metal material Substances 0.000 claims abstract description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000008239 natural water Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003643 water by type Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 하부 금속배선이 형성된 제1 층간 절연막 상부에 확산 방지막, 제2 층간 절연막, 제3 층간 절연막을 순차적으로 형성하는 단계, 상기 제3 층간 절연막을 포함한 결과물 상에 비아홀을 정의하는 제1 포토레지스트 패턴을 형성하는 단계, 상기 제1 포토레지스트 패턴을 식각 마스크로 하여 상기 제3 층간 절연막을 식각하는 제1 식각 공정과 상기 제2 층간 절연막을 식각하는 제2 식각 공정을 순차적으로 수행하여 비아홀을 형성하는 단계, 상기 제1 포토레지스트 패턴을 제거한 후 상기 제3 층간 절연막 상부의 소정 영역에 금속배선 트렌치를 정의하는 제2 포토레지스트 패턴을 형성하고, 상기 제2 포토레지스트 패턴을 식각 마스크로 하여 제3 층간 절연막을 식각하여 금속배선 트렌치를 형성하는 단계 및 상기 금속배선 트렌치 및 비아홀에 금속물질을 매립하여 상기 하부 금속배선과 전기적으로 연결되는 상부 금속배선을 형성하는 단계를 포함하며, 상기 제2 식각 공정은 상기 제3 층간 절연막을 식각하는 제1 식각 공정에서 상기 제3 층간 절연막의 측벽에 생성된 플루오르 카본(fluorocarbon) 폴리머를 제거하기 위해 CxFy, N2, O2 및 Ar이 혼합된 가스 또는 CHpFp, CxFy, N2, O2 및 Ar이 혼합된 가스(여기서, x, y, p는 자연수)를 사용한다.The present invention relates to a method of forming a metal interconnection of a semiconductor device, the method comprising sequentially forming a diffusion barrier layer, a second interlayer insulation layer, a third interlayer insulation layer on the first interlayer insulation layer on which the lower metal interconnection is formed; Forming a first photoresist pattern defining a via hole on the resultant, a first etching process of etching the third interlayer insulating layer using the first photoresist pattern as an etching mask, and etching the second interlayer insulating layer Forming a via hole by sequentially performing a second etching process, and after removing the first photoresist pattern, forming a second photoresist pattern defining a metal wiring trench in a predetermined region on the third interlayer insulating layer; Forming a metal wiring trench by etching the third interlayer insulating layer using the second photoresist pattern as an etching mask; Forming a top metal wiring electrically connected to the bottom metal wiring by filling a metal material in the system and the metal wiring trench and the via hole, wherein the second etching process includes: a first etching the third interlayer insulating film; Gas mixed with CxFy, N2, O2 and Ar or gas mixed with CHpFp, CxFy, N2, O2 and Ar to remove the fluorocarbon polymer formed on the sidewall of the third interlayer insulating film in the etching process (where , x, y, and p are natural numbers).
금속배선, 플루오르 카본(fluorocarbon) 폴리머Metallization, fluorocarbon polymers
Description
도 1 내지 도 3은 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다.
1 to 3 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20: 제1 금속배선 22: 제1 층간 절연막20: first metal wiring 22: first interlayer insulating film
24: 확산 방지막 26: 제2 층간 절연막24: diffusion barrier film 26: second interlayer insulating film
28: 제3 층간 절연막 30: 제1 반사방지막28: third interlayer insulating film 30: first antireflection film
32: 제2 반사방지막
32: second antireflection film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
일반적으로 반도체 소자가 미세화됨에 따라 금속배선 간의 RC 딜레이가 큰 문제로 대두되었으며 이를 해결하기 위해 구리 금속배선과 저유전막질의 층간 절연막이 도입되었다. In general, as semiconductor devices have been miniaturized, the RC delay between metal wirings has become a big problem, and to solve this problem, copper metal wirings and low dielectric film interlayer insulating films have been introduced.
상기 구리 금속배선을 형성하기 위해 주로 듀얼 다마신 공정을 주로 사용하게 되는 데, 상기 듀얼 다마신 공정을 통해 구리 금속배선을 형성할 때는 저유전막질의 층간 절연막 사이에 식각정지막들을 형성하여 통일성을 가진 금속배선 저항을 확보할 수 있게 된다. The dual damascene process is mainly used to form the copper metal interconnection. When the copper metal interconnection is formed through the dual damascene process, etching stop layers are formed between the interlayer insulating layers of low dielectric film quality to have uniformity. Metal wiring resistance can be secured.
그러나 최근 들어 식각 정지막의 사용에 제한이 따르게 되어 식각 정지막을 사용하지 않고 비아 레벨과 트렌치 레벨의 층간 절연막들을 서로 다르게 적용하여 금속배선을 형성하는 하이브리드(hybrid) 듀얼 다마신 공정이 도입되었는 데, 이때 주로 트렌치 레벨의 층간 절연막으로는 저유전막질을, 비아 레벨의 층간 절연막들로는 FSG와 같은 막질을 사용하게 된다. However, in recent years, the use of an etch stop film has been restricted, and a hybrid dual damascene process, in which a metallization is formed by applying different via and trench level interlayer insulating films without using an etch stop film, has been introduced. In general, a low dielectric film quality is used as the trench level interlayer insulating film, and a film quality such as FSG is used as the via level interlayer insulating film.
그러나 상기 하이브리드 듀얼 다마신 공정에 비아 홀 형성을 위한 식각 공정시 식각가스로 CxFy, O2, 및 Ar이 혼합된 가스 또는 CHpFp, CxFy, O2 및 Ar이 혼합된 가스(여기서, x, y, p는 자연수)를 사용하여 수행하였는데, 저유전막질인 층간 절연막의 식각시에는 플루오르 카본(fluorocarbon) 폴리머가 다량으로 형성되어 비아홀 내부에 증착하게 되어 계속적으로 수행되는 FSG막인 층간 절연막의 식각이 정지되어 비아홀의 형성을 방해하는 문제점이 있었다. However, in the hybrid dual damascene process, a gas containing CxFy, O2, and Ar mixed as an etching gas or a gas mixed with CHpFp, CxFy, O2 and Ar as an etching gas in the etching process for forming a via hole (where x, y, p is When the interlayer insulating film is a low dielectric film, a large amount of fluorocarbon polymer is formed and deposited inside the via hole, so that the etching of the interlayer insulating film, which is a continuous FSG film, is stopped. There was a problem that prevented formation.
상술한 문제점을 해결하기 위한 본 발명의 목적은 비아홀의 형성을 방해하는 요소가 제거된 반도체 소자의 금속배선 형성방법을 제공함에 있다.
An object of the present invention for solving the above problems is to provide a method for forming a metal wiring of a semiconductor device in which the element that prevents the formation of the via hole is removed.
상술한 목적을 달성하기 위한 본 발명의 사상은 하부 금속배선이 형성된 제1 층간 절연막 상부에 확산 방지막, 제2 층간 절연막, 제3 층간 절연막을 순차적으로 형성하는 단계, 상기 제3 층간 절연막을 포함한 결과물 상에 비아홀을 정의하는 제1 포토레지스트 패턴을 형성하는 단계, 상기 제1 포토레지스트 패턴을 식각 마스크로 하여 상기 제3 층간 절연막을 식각하는 제1 식각 공정과 상기 제2 층간 절연막을 식각하는 제2 식각 공정을 순차적으로 수행하여 비아홀을 형성하는 단계, 상기 제1 포토레지스트 패턴을 제거한 후 상기 제3 층간 절연막 상부의 소정 영역에 금속배선 트렌치를 정의하는 제2 포토레지스트 패턴을 형성하고, 상기 제2 포토레지스트 패턴을 식각 마스크로 하여 제3 층간 절연막을 식각하여 금속배선 트렌치를 형성하는 단계 및 상기 금속배선 트렌치 및 비아홀에 금속물질을 매립하여 상기 하부 금속배선과 전기적으로 연결되는 상부 금속배선을 형성하는 단계를 포함하며, 상기 제2 식각 공정은 상기 제3 층간 절연막을 식각하는 제1 식각 공정에서 상기 제3 층간 절연막의 측벽에 생성된 플루오르 카본(fluorocarbon) 폴리머를 제거하기 위해 CxFy, N2, O2 및 Ar이 혼합된 가스 또는 CHpFp, CxFy, N2, O2 및 Ar이 혼합된 가스(여기서, x, y, p는 자연수)를 사용한다.
상기 제2 층간 절연막은 FSG막 또는 TEOS막으로 형성한다.
상기 제3 층간 절연막은 k가 3이하인 저유전율 막질로 형성한다.
상기 제1 식각공정은 CxFy, O2 및 Ar이 혼합된 가스(여기서, x, y는 자연수)를 사용하여 수행한다.The idea of the present invention for achieving the above object is the step of sequentially forming a diffusion barrier film, a second interlayer insulating film, a third interlayer insulating film on top of the first interlayer insulating film formed with the lower metal wiring, the resultant including the third interlayer insulating film Forming a first photoresist pattern defining a via hole on the substrate, a first etching process of etching the third interlayer insulating layer using the first photoresist pattern as an etching mask, and a second etching of the second interlayer insulating layer Forming a via hole by sequentially performing an etching process, and after removing the first photoresist pattern, forming a second photoresist pattern defining a metal wiring trench in a predetermined region on the third interlayer insulating layer; Etching the third interlayer insulating layer using the photoresist pattern as an etching mask to form a metal wiring trench; and Forming an upper metal wiring electrically connected to the lower metal wiring by filling a metal material in a fast trench and via hole, wherein the second etching process is performed in a first etching process of etching the third interlayer insulating layer. Gas mixed with CxFy, N2, O2 and Ar or mixed with CHpFp, CxFy, N2, O2 and Ar to remove the fluorocarbon polymer formed on the sidewall of the third interlayer insulating film (where x, y and p are natural numbers).
The second interlayer insulating film is formed of an FSG film or a TEOS film.
The third interlayer insulating film is formed of a low dielectric constant film having k of 3 or less.
The first etching process is performed using a gas in which CxFy, O2 and Ar are mixed (where x and y are natural water).
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이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1 내지 도 3은 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 3 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
도 1을 참조하면, 구리물질과 같은 금속배선(20)이 형성된 제1 층간 절연막(22) 상부에 확산 방지막(24), 제2 층간 절연막(26), 제3 층간 절연막(28) 및 제1 반사방지막(30)을 순차적으로 형성한다. Referring to FIG. 1, the
상기 제2 층간 절연막(26)은 FSG막 또는 TEOS막으로 형성할 수 있고, 상기 제3 층간 절연막(28)은 k가 3이하인 저유전율 막질로 형성할 수 있다.
The second interlayer
상기 제3 층간 절연막(28) 상에 비아홀을 정의할 제1 포토레지스트 패턴(PR1)을 형성하고, 이를 식각 마스크로 제1 반사방지막(30), 제3 층간 절연막(28) 및 제2 층간 절연막(26)을 식각하여 비아홀(VH)을 형성한다. A first photoresist pattern PR1 defining a via hole is formed on the third
상기 비아홀(VH) 형성 식각 공정시 제3 층간 절연막(28)까지의 식각공정과 제2 층간 절연막(26)의 식각공정을 각각 수행하게 된다. In the etching process of the via hole VH formation, the etching process up to the third
상기 제3 층간 절연막(28)의 식각 공정은 CxFy, O2, 및 Ar이 혼합된 가스(여기서, x, y는 자연수)를 사용하여 수행하는 데, 이 식각공정으로 인해 제3 층간 절연막(28)에 형성된 비아홀의 측벽에는 플루오르 카본(fluorocarbon)폴리머가 생성되고, 이로 인해 제2 층간 절연막(26)에는 식각이 수행되지 않아 식각이 정지된다. The etching process of the third
이어서, 식각이 정지된 상기 제2 층간 절연막(26)에 또 다른 식각가스를 통해 식각공정을 수행하게 되는 데, 이때 식각가스는 CxFy, N2, O2 및 Ar이 혼합된 가스 또는 CHpFp, CxFy, N2, O2 및 Ar이 혼합된 가스(여기서, x, y, p는 자연수)를 사용하여 수행하는 데, 이 식각공정으로 인해 제3 층간 절연막(28)의 식각시 형성된 플루오르 카본 폴리머를 제거하면서 동시에 제2 층간 절연막(26)을 식각하여 비아홀(VH)의 형성을 완료한다.Subsequently, the etching process is performed through another etching gas to the second
종래 기술에서와 같이 저유전막질인 제3 층간 절연막 및 FSG막인 제2 층간절연막에 CxFy, O2 및 Ar이 혼합된 가스 또는 CHpFp, CxFy, Ar, O2이 혼합된 가스(여기서, x, y, p는 자연수)를 통해 식각공정을 수행하게 되면, 제3 층간 절연막의 식각시 플루오르 카본(fluorocarbon)폴리머의 생성이 심하게 되어 FSG막인 제2 층간 절연막의 식각이 정지되는 문제점이 있었지만, 본 발명에서와 같이 N2를 첨가된 식각가스를 통해 제2 층간 절연막의 식각을 진행하게 되면, CNFx와 같은 형태로 플루오로 카본(fluorocarbon)폴리머가 제거되어 FSG막인 제2 층간 절연막의 식각도 원할히 수행되었다.As in the prior art, a gas in which CxFy, O2 and Ar are mixed or a gas in which CHpFp, CxFy, Ar, and O2 are mixed in a third interlayer insulating film having a low dielectric film quality and a second interlayer insulating film which is an FSG film (here, x, y, p When the etching process is performed through a natural number), the fluorocarbon polymer is severely generated during the etching of the third interlayer insulating film, so that the etching of the second interlayer insulating film, which is the FSG film, is stopped. When the second interlayer insulating film was etched through the etching gas to which N2 was added, the fluorocarbon polymer was removed in the same form as CNFx, thereby smoothly etching the second interlayer insulating film, which is an FSG film.
도 2를 참조하면, 상기 비아홀(VH)이 형성된 결과물의 제1 포토레지스트 패턴(PR1) 및 제1 반사방지막(30)을 제거하고, 상기 제3 층간 절연막(28) 상에 제2 반사 방지막(32)을 형성하고, 제2 반사 방지막(32)상의 소정 영역에 금속배선 트렌치를 정의하는 제2 포토레지스트 패턴(PR2)을 형성하고 이를 식각 마스크로 제2 반사방지막(32) 및 제3 층간절연막(28)을 식각하여 금속배선 트렌치(MT)를 형성한다. Referring to FIG. 2, the first photoresist pattern PR1 and the first
상기 금속배선 트렌치를 정의하기 위한 상기 제3 층간 절연막의 식각 공정시하부의 FSG막인 제2 층간 절연막이 식각되지 않도록 하기 위해, CxFy, N2, 및 Ar이 혼합된 가스(여기서, x, y는 자연수)를 식각가스로 하여 수행한다. In order to prevent the second interlayer insulating film, which is the FSG film during the etching process of the third interlayer insulating film, to define the metallization trench from being etched, a gas in which CxFy, N2, and Ar are mixed (where x and y are natural numbers ) As an etching gas.
상기 금속배선 트렌치 공정시 비아 바텀 부위의 확산반지막이 식각되어 하부의 금속배선이 노출되지 않도록 한다. During the metallization trench process, the diffusion ring layer of the via bottom portion is etched to prevent the lower metallization from being exposed.
도 3을 참조하면, 상기 형성된 금속배선 트렌치(MT) 및 비아홀(VH)에 금속물질을 형성하여 금속배선 및 비아의 형성을 완료한다. Referring to FIG. 3, a metal material is formed in the formed metal wiring trench MT and the via hole VH to complete formation of the metal wiring and the via.
본 발명에 의하면, 스퍼터 비율이 높은 N2 이온이 첨가된 식각가스를 통해 제3 층간 절연막의 식각, 제2 층간 절연막의 식각을 각각 진행하게 되면, 플루오르 카본(fluorocarbon)폴리머가 제거되어 FSG막인 제2 층간 절연막의 식각도 원할히 수행하여, 비아홀의 형성을 방해하는 요소가 제거된다.
According to the present invention, when the etching of the third interlayer insulating film and the etching of the second interlayer insulating film are performed through the etching gas to which N2 ions having a high sputter ratio are added, the fluorocarbon polymer is removed to form the second FSG film. Etching of the interlayer insulating film is also performed smoothly, so that the elements which prevent the formation of the via holes are removed.
이상에서 살펴본 바와 같이 본 발명에 의하면, 스퍼터 비율이 높은 N2 이온이 첨가된 식각가스를 통해 제3 층간 절연막의 식각, 제2 층간 절연막의 식각을 각각 진행하게 되면, 플루오르 카본(fluorocarbon)폴리머가 제거되어 FSG막인 제2 층간 절연막의 식각도 원할히 수행하여, 비아홀의 형성을 방해하는 요소가 제거되는 효과가 있다. As described above, according to the present invention, when the etching of the third interlayer insulating film and the etching of the second interlayer insulating film are performed through the etching gas to which the N2 ion having a high sputter ratio is added, the fluorocarbon polymer is removed. As a result, etching of the second interlayer insulating film, which is the FSG film, is also performed smoothly, thereby removing the elements that prevent the formation of the via holes.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
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| KR20010019643A (en) * | 1999-08-28 | 2001-03-15 | 윤종용 | Method for manufacturing multilevel metal interconnections having low dielectric constant insulator |
| KR20010072874A (en) * | 1999-06-30 | 2001-07-31 | 리차드 로브그렌 | Dual-damascene dielectric structures and methods for making the same |
| KR20030006241A (en) * | 2001-07-12 | 2003-01-23 | 삼성전자 주식회사 | Method for forming wiring using dual damacine process |
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| KR20010072874A (en) * | 1999-06-30 | 2001-07-31 | 리차드 로브그렌 | Dual-damascene dielectric structures and methods for making the same |
| KR20010019643A (en) * | 1999-08-28 | 2001-03-15 | 윤종용 | Method for manufacturing multilevel metal interconnections having low dielectric constant insulator |
| KR20030006241A (en) * | 2001-07-12 | 2003-01-23 | 삼성전자 주식회사 | Method for forming wiring using dual damacine process |
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