KR20050017844A - Method of forming a dual damascene pattern - Google Patents

Abstract

PURPOSE: A method for forming a dual damascene pattern is provided to prevent a via faceting phenomenon and a via bowing phenomenon caused by a difference of a via hole density and avoid an increase of the dielectric constant of a low-k interlayer dielectric by preventing the low-k interlayer dielectric and a lower interconnection from being exposed to oxygen plasma used for removing an organic bottom ARC(anti-reflective coating). CONSTITUTION: A diffusion barrier layer(12), an interlayer dielectric(13) and a capping layer(14) are formed on a substrate(10) having an interconnection. The exposed portions of the capping layer and the interlayer dielectric are etched to form a via hole(16) by a via hole etch process. A nitride spacer is formed on the sidewall of the via hole. An organic bottom ARC is formed on the resultant structure. The exposed portions of the organic bottom ARC, the capping layer and the interlayer dielectric are etched by a predetermined depth to form a trench(19) by a trench etch process. The nitride spacer is removed. The diffusion barrier layer exposed to the bottom of the via hole is eliminated.

Description

Method of forming a dual damascene pattern

The present invention relates to a method for forming a dual damascene pattern, and more particularly, to a method for forming a dual damascene pattern by a via first method.

In general, as the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of devices continues to shrink into the sub-half-micron area, while improving performance and reliability. In terms of circuit density, circuit density is increasing. In response to these demands, the copper thin film has a higher melting point than aluminum in forming metal wirings of the semiconductor device, and thus has high resistance to electro-migration (EM), thereby improving reliability of the semiconductor device and providing a specific resistance. This low rate can increase the signal transfer rate, making it a useful interconnect material for integration circuits. In addition, as semiconductor devices have been highly integrated and technology has been developed, parasitic capacitors between wirings have become a problem, and low dielectric constant (Low-k) having a dielectric constant value of 3 or less, such as porous oxide, is a material of an interlayer insulating film. Insulation material is used.

However, in proceeding the wiring process using an insulating material of copper and a low dielectric constant value, the dual damascene process has recently been widely applied to solve this problem because the etching characteristics of copper are very poor.

The dual damascene process is carried out in a variety of ways, which can be summarized in four ways: buried vias, via first, trench first, and self-aligned. .

In the conventional dual damascene pattern formation method using the via first method, a via hole is first formed in a low dielectric interlayer insulating film, a via hole is filled with an organic bottom anti-reflective coating (organic B-ARC), and a low dielectric interlayer insulating film A trench etch stop layer formed therein is applied to form the trench. By the way, the via holes are formed in a single circuit by the circuit design, or are formed in various densities, or have different hole sizes, and thus have different pattern densities. do. Via faceting and via bowing may occur due to the difference in thickness of the organic bottom-anti-reflective coating that is filled in the via holes, which causes distortion of the pattern profile during the trench etching process. In addition, it is difficult to set the etching conditions, as well as the deposition of a barrier layer and a copper seed layer on the dual damascene pattern, making copper filling difficult. In addition, since the organic bottom anti-reflection film is strong cross-rinking due to high temperature curing and does not melt in a chemical material, the organic bottom anti-reflection film can be removed by using an O ₂ plasma. In general, however, low-k dielectrics are degraded when exposed to O ₂ plasma. In addition, when the lower wiring is exposed to O ₂ plasma, damage is caused. In particular, when the lower wiring is formed of copper, oxidation proceeds to form CuO, which lowers electrical characteristics of the copper lower wiring. Furthermore, internal capacitance is formed by forming a trench etch stop layer made of a material such as oxide and nitride having a relatively higher dielectric constant than the low dielectric interlayer insulating film in order to maintain a lower via profile during trench etching. Is increased to deteriorate the characteristics of the device.

Accordingly, the present invention prevents the occurrence of via-passing and via-bowing due to the difference in via hole density generated in the via first dual damascene process, and the low dielectric interlayer in the O ₂ plasma used to remove the organic bottom anti-reflection film. By preventing the insulating film and the lower wiring from being exposed, it is possible to prevent the dielectric constant of the low dielectric interlayer insulating film and damage to the lower wiring, and to prevent the internal capacitance from increasing by forming a relatively high dielectric constant trench etch stop layer in the low dielectric interlayer insulating film. Accordingly, an object of the present invention is to provide a dual damascene pattern formation method capable of improving the reliability of metal wiring.

The dual damascene pattern forming method of the present invention for achieving the above object comprises the steps of forming a diffusion barrier, an interlayer insulating film and a capping layer on the substrate formed wiring; Forming via holes by etching exposed portions of the capping layer and the interlayer insulating layer through a via hole etching process; Forming a nitride spacer on a sidewall of the via hole; Forming an organic bottom anti-reflection film on the entire structure including the via hole in which the nitride spacer is formed; Etching the exposed portions of each of the organic bottom-anti-reflection film, the capping layer, and the interlayer insulating film by a trench etching process to form a trench; Removing the nitride spacers; And removing the diffusion barrier exposed on the bottom of the via hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

1A to 1H are cross-sectional views of devices for describing a dual damascene pattern forming method according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 10 having a lower wiring 11 is provided, and a diffusion barrier film 12 is formed on the entire structure including the lower wiring 11. An interlayer insulating film 13 and a capping layer 14 are formed on the diffusion barrier 12. A photoresist pattern 15 for a via hole is formed on the capping layer 14 in which a region in which the via hole is to be formed is opened. An exposed portion of each of the capping layer 14 and the interlayer insulating layer 13 is etched by a via etching process using the photoresist pattern 15 for the via hole as an etching mask to form the via hole 16 having the diffusion barrier 12 exposed thereon. do.

In the above, the diffusion barrier 12 serves to prevent oxidation of copper and external diffusion of copper ions when the lower wiring 11 is copper, and protects the lower wiring 11 when forming a via hole to be formed by a subsequent process. It plays a role. The diffusion barrier 12 is typically formed using a nitride series, but in this case, SiC having a dielectric constant lower than that of the nitride series is deposited by PE-CVD to a thickness of 300 to 500 kW in order to prevent an increase in internal capacitance. In order to solve the problem caused by the parasitic capacitor between the wiring and the wiring, the interlayer insulating layer 13 is a material in which H, F, C, CH _3, etc. are partially coupled to SiO ₂ series having a dielectric constant value of 1.5 to 4.5 band. However, organic materials such as CHLK-based polymer-based SiLK ^TM products and Flare ^TM products, or porous materials having increased porosity in order to lower the dielectric constant of these materials ( porous) It is formed to a thickness of 7000 ~ 9000Å. The capping layer 14 is formed by depositing an oxide to a thickness of 800 to 1200 Å by PE-CVD in order to prevent moisture absorption of the low dielectric interlayer insulating layer 13 or damage caused by a subsequent process. It can be formed using a nitride such as -TEOS, SiN, SiON, Si ₃ N ₄ . The via hole 16 is formed by etching the interlayer insulating film 13 by using a plasma activated with a C ₄ F ₈ gas, an N ₂ gas, and an Ar gas, or N for protecting the interlayer insulating film 13 in an O ₂ gas. _It forms by etching the interlayer insulation film 13 using the plasma which combined ₂ gases.

Referring to FIG. 1B, the via hole photoresist pattern 15 is removed. The nitride film 100 is formed along the surface of the entire structure including the via hole 16. The nitride film 100 is formed by depositing nitride by using a PE-CVD method to protect the sidewalls of the via hole 16. The gases used are SiH ₄ , N ₂ and N ₂ O gases, and the deposition thickness Is formed by depositing to a thickness of 300 to 500Å in consideration of the via hole size and the via hole aspect ratio.

Referring to FIG. 1C, the nitride film 100 is etched by a blanket etch process to form nitride spacers 100S on the sidewalls of the via holes 16, thereby forming interlayers forming the sidewalls of the via holes 16. The insulating film 13 is protected.

In the above, the blanket etching process for forming the nitride spacer 100S uses an etching apparatus having a medium ion density (1 × 10 <11> ion / cm ³ ), and the conditions of the etching apparatus are used. Pressure of 50 to 70 mTorr, source power of 1500 to 1800 W and bias power of 200 to 500 W, and 30 to 50 sccm of CF ₄ , 10 to 20 sccm of CHF ₃ , 10 to 20 sccm of Proceed with O ₂ and 400 to 600 sccm of Ar.

Referring to FIG. 1D, an organic bottom-reflective film (organic Barc film) 17 is formed on the entire structure including the via hole 16 formed on the sidewall of the nitride spacer 100S, which is an inorganic bottom-reflective material. To form. A trench photoresist pattern 18 is formed on the organic bottom anti-reflection film 17.

In the above, the organic bottom anti-reflection film 17 is simultaneously etched during the trench etching process while preventing the bottom of the via hole 16 from being etched during the subsequent trench etching process, and 50 to 50 times the height of the via hole 16 by the rotation coating method. It is formed to a thickness of 500 to 1000 mm which is about 70%. The trench photoresist pattern 18 is formed using a deep UV resist.

Referring to FIG. 1E, the trench is formed by etching the exposed portions of the organic bottom anti-reflection film 17, the capping layer 14, and the interlayer insulating layer 13 using a trench photoresist pattern 18 as an etching mask. (19) is formed. Thereafter, the trench photoresist pattern 18 and the remaining organic bottom anti-reflection film 17 are removed. On the other hand, the trench photoresist pattern 18 and the organic bottom anti-reflection film 17 may be removed at the same time during the etching process for forming the trench 19 without being removed in a separate process, which will be described below. .

In the above, an etching process for forming the trench 19 uses an etching apparatus having a medium ion density (1 × 10 <10> ion / cm ³ ), and the etching order is an organic bottom antireflection film ( 17)-> Capping layer (14)-> Interlayer insulating film (13) in this order.

First, the etching process of the organic bottom anti-reflection film 17 is carried out with the etching equipment conditions as a pressure of 10 to 20 mTorr, a source power of 1000 to 1500W and a bias power of 100 to 300W, and 20 to shed the 40sccm of O ₂ and N ₂ from 60 to 80sccm advances to ensure that little etching selectivity of the nitride ratio of infinity.

Next, the etching process of the capping layer 14 formed of oxide is set to the etching equipment conditions of 50 to 70mTorr pressure, source power of 1000 to 1500W and bias power of 300 to 500W, equipment 50 to 100 sccm of CF ₄ , 20 to 30 sccm of CHF ₃ , 10 to 20 sccm of O _2, and 400 to 600 sccm of Ar are run.

Finally, the etching process of the interlayer insulating film 13 formed of a polymer-based low dielectric material lowers the pressure to minimize the attack caused by the etching of the interlayer insulating film 13, thereby reducing the pressure of oxygen radicals. (residence time) is reduced, and N ₂ is added to passivation the side wall. The etching process of the interlayer insulating layer 13 to satisfy this can be divided into two types. The first etching process uses etching equipment conditions with a pressure of 10 to 20 mTorr, a source power of 1000 to 1500 W, and a bias power of 100 to 300 W, and 50 to 100 sccm of O ₂ and 200 to The flow proceeds by flowing 300 sccm of N ₂ . The second etching process uses etching equipment conditions with a pressure of 10 to 20 mTorr, a source power of 1000 to 1500 W and a bias power of 100 to 300 W, and 50 to 100 sccm of H ₂ and 200 to The flow proceeds by flowing 300 sccm of N ₂ . While the trench 19 is formed under the etching conditions described above, both the trench photoresist pattern 18 and the organic bottom anti-reflection film 17 are removed. When etching with only O ₂ plasma, the interlayer insulating film 13 made of a low dielectric polymer material is oxidized by oxygen-based active species on the sidewall of the trench 19 to form a deposition layer, and high incident ion energy is obtained to secure anisotropy. Inevitably, the nitride spacer 100S, which serves as a hard mask on the upper side, is greatly retracted. If N ₂ is used instead of O ₂ , there is no fear that the sidewalls after etching are oxidized and the reactivity between the active species in the plasma and the interlayer insulating film 13 is low, so that high ion energy is not required for anisotropic processing and serves as a hard mask. There is an advantage that the erosion of the nitride spacer 100S does not occur.

Referring to FIG. 1F, the nitride spacer 100 protecting the sidewall of the via hole 16 is selectively removed by performing a wet etching process with an H ₃ PO ₄ aqueous solution. At this time, the H ₃ PO ₄ aqueous solution used in the nitride spacer (100S) removal process is maintained at a high temperature of 150 to 200 ℃, mix 10 to 20% H ₂ O with 80 to 90% H ₃ PO ₄ . .

Referring to FIG. 1G, the diffusion barrier layer 12 exposed on the bottom surface of the via hole 16 is removed to expose the lower wiring 11. In the case where the diffusion barrier 12 is formed of SiC, the etching conditions are set to minimize the etching damage to the interlayer insulating layer 13 while leaving the capping layer 14. The etching equipment conditions are set at a pressure of 30 to 50 mTorr, 1000 Source power from 1500W to 1500W and bias power from 100 to 300W, and 20 to 30 sccm CHF ₃ , 20 to 30 sccm O ₂ , 50 to 100 sccm N ₂ and 400 to 600 sccm Proceed with Ar.

Referring to FIG. 1H, the upper interconnection 20 connected to the lower interconnection 11 is formed in the dual damascene pattern including the via hole 16 and the trench 19. The upper wiring 20 may be formed of a conductive material used as a wiring material of a semiconductor device such as copper, tungsten, aluminum, or the like.

As described above, in the present invention, after forming the via hole in the via first method among the dual damascene pattern forming methods, a nitride spacer is formed on the sidewalls of the via holes to protect the via hole sidewalls, and the via holes on which the nitride spacers are formed are organic bottoms. After filling with anti-reflection film and performing trench etching process and organic bottom anti-reflection film removal process, the remaining nitride spacers are selectively removed without damaging the low dielectric constant interlayer insulating film to form a dual damascene pattern consisting of via holes and trenches. To prevent via-passing and via-bowing due to the difference in via hole density generated in the via first dual damascene process, and to the low dielectric interlayer insulating film and lower wiring in the O ₂ plasma used to remove the organic bottom anti-reflection film. To prevent this exposure The dielectric constant of the interlayer insulating film and the damage of the lower wiring are prevented, and since the trench etch stop layer having a relatively high dielectric constant is not formed in the low dielectric interlayer insulating film, the internal capacitance is prevented from increasing, thereby improving the reliability of the metal wiring. .

1A to 1H are cross-sectional views of devices for describing a dual damascene pattern forming method according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: substrate 11: lower wiring

12: diffusion barrier film 13: interlayer insulating film

14 capping layer 15 photoresist pattern for via hole

16: Via Hole 17: Organic Bottom Anti-Reflective Film

18: photoresist pattern for trench 19: trench

20: upper wiring 100: nitride film

100S: Nitride spacer

Claims (11)

Forming a diffusion barrier film, an interlayer insulating film, and a capping layer on the wiring formed substrate; Forming via holes by etching exposed portions of the capping layer and the interlayer insulating layer through a via hole etching process; Forming a nitride spacer on a sidewall of the via hole; Forming an organic bottom anti-reflection film on the entire structure including the via hole in which the nitride spacer is formed; Etching the exposed portions of each of the organic bottom-anti-reflection film, the capping layer, and the interlayer insulating film by a trench etching process to form a trench; Removing the nitride spacers; And And removing the diffusion barrier exposed on the bottom of the via hole. The method of claim 1, wherein the diffusion barrier layer is formed by depositing SiC by PE-CVD. The _dual hole of claim 1, wherein the via hole is formed by etching the interlayer insulating layer by using a plasma activated with a C ₄ F ₈ gas, an N ₂ gas, and an Ar gas, or by combining N ₂ gas with an O ₂ gas. How to form a drank pattern. The method of claim 1, wherein after the nitride spacer is deposited by a PE-CVD method, the conditions of the etching equipment is a pressure of 50 to 70mTorr, source power of 1500 to 1800W and bias power of 200 to 500W, A method of forming a dual damascene pattern by flowing 30 to 50 sccm of CF ₄ , 10 to 20 sccm of CHF ₃ , 10 to 20 sccm of O _2, and 400 to 600 sccm of Ar to form a blanket etching process. The method of claim 1, wherein the organic bottom anti-reflection film is formed to a thickness of about 50 to 70% of the height of the via hole by a rotation coating method. The method of claim 1, wherein the organic bottom anti-reflective film has an etching equipment conditions of 10 to 20mTorr pressure, 1000 to 1500W source power and 100 to 300W bias power, 20 to 40sccm O ₂ and 60 to A method of forming a dual damascene pattern by etching 80 sccm of N ₂ . The method of claim 1, wherein the capping layer is formed of an oxide, the etching equipment conditions are 50 to 70mTorr pressure, 1000 to 1500W source power and 300 to 500W bias power, 50 to 100 sccm CF ₄ , A method of forming a dual damascene pattern by etching 20 to 30 sccm of CHF ₃ , 10 to 20 sccm of O _2, and 400 to 600 sccm of Ar. The method of claim 1, wherein the interlayer insulating film is formed of a polymer-based low dielectric material, and the etching equipment conditions are 10 to 20mTorr pressure, 1000 to 1500W source power and 100 to 300W bias power, 50 to within the equipment A method of forming a dual damascene pattern for etching by flowing 100 sccm of O ₂ and 200 to 300 sccm of N ₂ , or flowing 50 to 100 sccm of H ₂ and 200 to 300 sccm of N ₂ . The method of claim 1, wherein the nitride spacer is removed by a wet etching process using an H ₃ PO ₄ aqueous solution. The dual die of claim 9, wherein the H ₃ PO ₄ aqueous solution is maintained at a temperature of 150 to 200 ° C., and 80 to 90% of H ₃ PO ₄ is mixed with 10 to 20% of H ₂ O. 11. How to form a drank pattern. According to claim 1 or 2, wherein the diffusion barrier SiC is etching equipment conditions of 30 to 50mTorr pressure, 1000 to 1500W source power and 100 to 300W bias power, 20 to 30sccm CHF _{3 in the} equipment , 20 to 30 sccm O ₂ , 50 to 100 sccm N ₂ and 400 to 600 sccm Ar to remove the dual damascene pattern forming method.