JP2804543B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2804543B2
JP2804543B2 JP27376889A JP27376889A JP2804543B2 JP 2804543 B2 JP2804543 B2 JP 2804543B2 JP 27376889 A JP27376889 A JP 27376889A JP 27376889 A JP27376889 A JP 27376889A JP 2804543 B2 JP2804543 B2 JP 2804543B2
Authority
JP
Japan
Prior art keywords
interlayer insulating
insulating film
resist
bpsg
positive resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP27376889A
Other languages
Japanese (ja)
Other versions
JPH03136317A (en
Inventor
幸雄 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP27376889A priority Critical patent/JP2804543B2/en
Publication of JPH03136317A publication Critical patent/JPH03136317A/en
Application granted granted Critical
Publication of JP2804543B2 publication Critical patent/JP2804543B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、層間絶縁膜に対するポジレジストの密着
性を向上させ製品々質を向上させるようにした半導体素
子の製造方法に関するものである。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device in which the adhesion of a positive resist to an interlayer insulating film is improved to improve the quality of products.

(従来の技術) 第2図は、従来の層間絶縁膜として、硼−燐珪酸ガラ
ス(以下BPSGと云う)を用いた1MビットDRAMの半導体素
子の製造工程図である。
(Prior Art) FIG. 2 is a manufacturing process diagram of a 1-Mbit DRAM semiconductor element using boro-phosphosilicate glass (hereinafter referred to as BPSG) as a conventional interlayer insulating film.

先づシリコンウェハ21上に常法により下部パターン22
を形成する。次に層間絶縁膜としてBPSG膜23を常圧CVD
装置により8000Å生成させ、更に生成膜結晶化のために
拡散炉中で950℃,N2雰囲気にてアニール処理(BPSGフロ
ー)を行う(第2図a)。上記BPSG膜23の下部のパター
ン22と上部に形成されるパターン(図示せず)との電気
的接続のためのコンタクトウィンドを以下のホトリソ工
程により形成する。
First, a lower pattern 22 is formed on a silicon wafer 21 by a conventional method.
To form Next, a BPSG film 23 as an interlayer insulating film is subjected to normal pressure CVD.
8000 ° C is generated by the apparatus, and an annealing treatment (BPSG flow) is performed in a diffusion furnace at 950 ° C. in an N 2 atmosphere for crystallizing the formed film (FIG. 2a). A contact window for electrical connection between the lower pattern 22 of the BPSG film 23 and the upper pattern (not shown) is formed by the following photolithography process.

第2図(b)の如く、ポジレジスト24を12000Å塗布
し、ステッパによるマスク合せ及び露光を行い、テトラ
メチレンアンモニウムハイドロオキサイド(TMAH)系の
現像液、具体的には商品名NSD−TD(東京応化製)にて
ウェット現像を行いレジストパターン24aを得る(第2
図b,c,d)。尚図において25はマスク、26は紫外線を示
す。
As shown in FIG. 2 (b), a positive resist 24 is coated at 12000.degree., Mask alignment and exposure are performed by a stepper, and a tetramethylene ammonium hydroxide (TMAH) -based developer, specifically, a trade name NSD-TD (Tokyo, Japan) Resist pattern 24a by wet development (2nd
Figures b, c, d). In the drawing, reference numeral 25 denotes a mask, and 26 denotes ultraviolet rays.

得られたレジストパターン24aをマスクとして、常法
によりHF系エッチング液による符号27で示すウェットエ
ッチング部(通常4000Åエッチング)、更にRIE方式ド
ライエッチャによるドライエッチング部28を形成し、レ
ジストを除去して上記BPSG膜23にコンタクトウィンド29
を開口させるのである(第2図e,f,g)。
Using the obtained resist pattern 24a as a mask, a wet-etched portion (usually 4000 ° etching) indicated by reference numeral 27 using an HF-based etchant and a dry-etched portion 28 using a RIE dry etcher are formed by a conventional method, and the resist is removed. Contact window 29 on BPSG film 23
Are opened (FIGS. 2, e, f, g).

(発明が解決しようとする課題) しかしながら以上述べた方法においては、上記BPSG膜
の層間絶縁膜とその上に塗布されるポジレジストとの密
着性が充分でなく、その結果、その後の処理中、ホトリ
ソ工程でのウェット現像で上記BPSG膜とポジレジスト間
に現像液が侵入してレジストの剥離を招き、又更に上述
のウェットエッチングでHF系エッチング液が侵入して同
様にレジスト剥離を生じ、その結果ウェットエッチング
時に上記コンタクトウィンドにサイドエッチが発生し必
要以上に大きく開口されるに到るという問題かあった。
(Problems to be Solved by the Invention) However, in the method described above, the adhesion between the interlayer insulating film of the BPSG film and the positive resist applied thereon is not sufficient, and as a result, during the subsequent processing, In the wet development in the photolithography process, the developer penetrates between the BPSG film and the positive resist and causes peeling of the resist. As a result, there is a problem that side etching occurs in the contact window at the time of wet etching, and an opening larger than necessary is obtained.

この発明は、かかる層間絶縁膜とポジレジストとの密
着性が不充分であることにより発生する、上記ウェット
現像時のレジスト剥離、及びウェットエッチング時の必
要以上のコンタクトウィンドのサイドエッチを防止する
ことを目的とする。
An object of the present invention is to prevent the peeling of the resist at the time of the wet development and the unnecessary side etching of the contact window at the time of the wet etching, which are caused by insufficient adhesion between the interlayer insulating film and the positive resist. With the goal.

(課題を解決するための手段) この発明は、層間絶縁膜としてBPSG,燐珪酸ガラス
(以下PSG),硼珪酸ガラス(以下BSG)膜を使用する半
導体素子の製造にあたって、上記層間絶縁膜生成後、ポ
ジレジスト形成に先立ち、熱流酸過酸化水素又は熱硫酸
による洗浄等の処理工程を導入し、その後にコンタクト
ウィンドパターン形成のためのホトリソ、エッチングを
行なうようにしたものである。
(Means for Solving the Problems) The present invention relates to a method of manufacturing a semiconductor device using a BPSG, phosphosilicate glass (hereinafter, PSG), or borosilicate glass (hereinafter, BSG) film as an interlayer insulating film. Prior to the formation of a positive resist, a processing step such as washing with hot acid hydrogen peroxide or hot sulfuric acid is introduced, and then photolithography and etching for forming a contact window pattern are performed.

(作 用) この発明においては、上述のBPSG,PSG,BSG層間絶縁膜
に対してポジレジスト形成に先立ち熱硫酸等による処理
を行うことにより、該層間絶縁膜表面のガラス面特性に
何等かの変化を起し、これがポジレジストとの密着性向
上に寄与するものと考えられる。
(Operation) In the present invention, the above-mentioned BPSG, PSG, BSG interlayer insulating film is subjected to a treatment with hot sulfuric acid or the like prior to the formation of a positive resist, so that the glass surface characteristics of the surface of the interlayer insulating film have some characteristics. It is thought that this causes a change, which contributes to the improvement of the adhesion to the positive resist.

(実施例) 第1図にもとづきこの発明の実施例を説明する。上記
従来例で説明したように、先づBPSG膜の生成のために、
常圧CVD装置を用いて温度400℃,O2雰囲気SiH4,B2H6ガス
を用いて下部パターン2を予め形成したシリコンウェハ
1上にBPSG膜3を8000Å生成した。その後該BPSG膜3を
結晶化するため拡散炉にて950℃,15分間N2ガス条件にて
アニール(BPSGフロー)処理を行った(第1図a)。BP
SGフロー後、加熱ヒータ11により125℃に加熱温調され
たH2SO4/H2O2液10を収容した処理槽9中に、ウェハキャ
リア12に支持されたシリコンウェハ1を5分間浸漬した
(第1図b)。次に処理槽9からシリコンウェハ1を引
き上げ、純水槽13中の純水14にて充分リンスを行い乾燥
を行った(第1図c)。乾燥したシリコンウェハ1につ
いては、上記と同様に行ってコンタクトウィンドを形成
した。即ち先づ第1図dの如く、シリコンウェハ1のBP
SG膜3上にポジレジスト4を12000Å塗布した。次にス
テッパ露光機を用い、ガラスマスク5を通して435nmの
紫外線6をポジレジスト4に照射を行ってポジレジスト
4の紫外線6が照射された部分を感光しウェット現像液
にてレジストパターン4aを形成した(第1図f)。
(Embodiment) An embodiment of the present invention will be described with reference to FIG. As described in the above conventional example, first for the generation of the BPSG film,
Using a normal pressure CVD apparatus, a BPSG film 3 was formed at a temperature of 400 ° C. in an O 2 atmosphere SiH 4 and B 2 H 6 gas on a silicon wafer 1 on which a lower pattern 2 was formed in advance at 8000 °. Thereafter, in order to crystallize the BPSG film 3, annealing (BPSG flow) was performed in a diffusion furnace at 950 ° C. for 15 minutes under N 2 gas conditions (FIG. 1a). BP
After the SG flow, the silicon wafer 1 supported by the wafer carrier 12 is immersed for 5 minutes in the processing tank 9 containing the H 2 SO 4 / H 2 O 2 liquid 10 heated to 125 ° C. by the heater 11. (Fig. 1b). Next, the silicon wafer 1 was lifted out of the processing tank 9 and thoroughly rinsed with pure water 14 in a pure water tank 13 and dried (FIG. 1c). With respect to the dried silicon wafer 1, a contact window was formed in the same manner as described above. That is, as shown in FIG.
A positive resist 4 was applied on the SG film 3 at 12000 °. Next, using a stepper exposure machine, the positive resist 4 was irradiated with ultraviolet rays 6 of 435 nm through the glass mask 5, the portions of the positive resist 4 irradiated with the ultraviolet rays 6 were exposed, and a resist pattern 4a was formed with a wet developing solution. (FIG. 1f).

得られたレジストパターン4aをマスクとして、常法に
よりフッ酸5%+フッ化アンモン95%エッチング液によ
るエッチングを行い符号7で示すウェットエッチング部
(4000Å)、更にRIE方式ドライエッチャによるCHF3/O2
ガスによるエッチングでドライエッチング部8を形成
し、レジストを除去して上記BPSG膜3にコンタクトウィ
ンド9を開口させた(第1図g,h,i)。
Using the obtained resist pattern 4a as a mask, etching is performed with a hydrofluoric acid 5% + ammonium fluoride 95% etching solution by a conventional method, a wet etching portion (4000 °) indicated by reference numeral 7, and CHF 3 / O 2 by a RIE dry etcher.
A dry etching portion 8 was formed by etching with gas, the resist was removed, and a contact window 9 was opened in the BPSG film 3 (FIGS. 1 g, h, and i).

上記の如くして得られた実施例品に関してその特性を
下表に示す。尚表中比較例は上述の熱硫酸−過酸化水素
処理を行わないものである。
The properties of the thus obtained example products are shown in the table below. Note that the comparative examples in the table are those in which the above-mentioned hot sulfuric acid-hydrogen peroxide treatment is not performed.

上表によれば実施例により現像時のレジスト剥離は激
減し、サイドエッチ量が著しく少なくなっていることが
明らかであった。
According to the above table, it is clear that the resist drastically decreases during the development and the side etch amount is remarkably reduced in the examples.

この発明において、上述の層間絶縁膜処理に際して、
熱硫酸及び熱硫酸−過酸化水素の温度については概ね70
℃,10分にて充分な効果が認められた。勿論処理時間の
短縮のためには温度を上昇させるのが良い。
In the present invention, in the above-described interlayer insulating film processing,
The temperature of hot sulfuric acid and hot sulfuric acid-hydrogen peroxide is approximately 70
A sufficient effect was observed at 10 ° C for 10 minutes. Of course, it is preferable to raise the temperature in order to shorten the processing time.

温度の上限は硫酸の場合には特にないが、過酸化水素
混合の場合はその沸点(150℃)を考慮して蒸発を避け
るよう150℃以下が望ましい。
The upper limit of the temperature is not particularly limited in the case of sulfuric acid, but in the case of mixed hydrogen peroxide, the temperature is preferably 150 ° C. or lower in consideration of its boiling point (150 ° C.) to avoid evaporation.

過酸化水素の混入比は体積比で約1/25が好適である。 The mixing ratio of hydrogen peroxide is preferably about 1/25 by volume.

次に上記層間絶縁膜との密着性向上は、現在用いられ
る殆んど全てのレジストに対して効果があった。具体的
には商品名ONPR−800,TSMR−8800(以下東京応化工業
製),MP−1400(シップレー社製)などである。
Next, the improvement of the adhesion to the interlayer insulating film was effective for almost all currently used resists. Specific examples include ONPR-800, TSMR-8800 (trade names, manufactured by Tokyo Ohka Kogyo) and MP-1400 (manufactured by Shipley).

(発明の効果) 以上詳細に説明したように、この発明によれば下部パ
ターン上のBPSG,PSG,BSG形成フロー後に、熱H2SO4又はH
4SO4/H2O2洗浄等の処理工程を導入したので、層間絶縁
膜とポジレジストの密着が著しく強固になるものであ
る。その結果ホトリソでのウェット現像時のレジスト剥
離防止、及びウェットエッチングでのレジスト剥離防
止、更にサイドエッチ量を小さく抑えられるので上記の
問題が解消され品質の安定及び歩留り向上が得られる効
果がある。
(Effects of the Invention) As described in detail above, according to the present invention, after the flow of forming BPSG, PSG, and BSG on the lower pattern, heat H 2 SO 4 or H
Since a treatment step such as 4 SO 4 / H 2 O 2 cleaning is introduced, the adhesion between the interlayer insulating film and the positive resist becomes extremely strong. As a result, the resist peeling during wet development with photolithography, the resist peeling during wet etching, and the amount of side etching can be reduced, so that the above-mentioned problems can be solved and the quality can be stabilized and the yield can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明実施例の工程図、第2図は従来方法の工
程図である。 1……シリコンウェハ、2……下部パターン、3……BP
SG膜、4……ポジレジスト、5……マスク、6……紫外
線、7……ウェットエッチ部、8……ドライエッチ部、
9……処理槽、10……H2SO4/H2O2、11……加熱ヒータ、
14……純水。
FIG. 1 is a process diagram of an embodiment of the present invention, and FIG. 2 is a process diagram of a conventional method. 1 ... silicon wafer, 2 ... lower pattern, 3 ... BP
SG film, 4 ... Positive resist, 5 ... Mask, 6 ... Ultraviolet, 7 ... Wet etch, 8 ... Dry etch,
9: treatment tank, 10: H 2 SO 4 / H 2 O 2 , 11: heater
14 ... Pure water.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】素子の層間絶縁膜として硼−燐珪酸ガラ
ス,燐珪酸ガラス又は硼珪酸ガラスを用いる半導体素子
の製造方法において、前記層間絶縁膜の生成後ポジレジ
スト塗布に先立ち、 層間絶縁膜面を熱硫酸又は熱硫酸−過酸化水素にて処理
する工程、 を導入することを特徴とする半導体素子の製造方法。
1. A method of manufacturing a semiconductor device using boro-phosphosilicate glass, phosphosilicate glass, or borosilicate glass as an interlayer insulating film of an element, wherein the surface of the interlayer insulating film is formed after the interlayer insulating film is formed and before a positive resist is applied. Treating the product with hot sulfuric acid or hot sulfuric acid-hydrogen peroxide.
JP27376889A 1989-10-23 1989-10-23 Method for manufacturing semiconductor device Expired - Lifetime JP2804543B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27376889A JP2804543B2 (en) 1989-10-23 1989-10-23 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27376889A JP2804543B2 (en) 1989-10-23 1989-10-23 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH03136317A JPH03136317A (en) 1991-06-11
JP2804543B2 true JP2804543B2 (en) 1998-09-30

Family

ID=17532310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27376889A Expired - Lifetime JP2804543B2 (en) 1989-10-23 1989-10-23 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2804543B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100269272B1 (en) * 1992-06-03 2000-10-16 윤종용 Method for manufacturing semiconductor device
KR0170270B1 (en) * 1995-12-30 1999-03-30 김광호 Profile-improving method of contact hole formed on the pospho-silicate glass
KR19980033871A (en) * 1996-11-02 1998-08-05 김광호 Manufacturing Method of Semiconductor Device

Also Published As

Publication number Publication date
JPH03136317A (en) 1991-06-11

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