KR100268859B1 - Method for forming metal interconnector of semiconductor device - Google Patents

Method for forming metal interconnector of semiconductor device Download PDF

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KR100268859B1
KR100268859B1 KR1019920012905A KR920012905A KR100268859B1 KR 100268859 B1 KR100268859 B1 KR 100268859B1 KR 1019920012905 A KR1019920012905 A KR 1019920012905A KR 920012905 A KR920012905 A KR 920012905A KR 100268859 B1 KR100268859 B1 KR 100268859B1
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film
sog
hld
substrate
sog film
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KR940002949A (en
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양대근
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal interconnect of a semiconductor device is provided to improve an Al step coverage by controlling an etch slope where the metal interconnect process is performed using a B2O3 and P2O5 SOG(Silicon On Glass) film. CONSTITUTION: An oxide is formed on a substrate(1), and a gate(2) is patterned on the oxide. Next, an HLD film(8) as thick as 9000 angstrom is deposited on the whole surface, and a B2O3 SOG film as thick as 1000 angstrom is coated. And, after coating a P2O5 film as thick as 3000 angstrom on the whole surface, a photo resist is formed on the surface except the revealed region of the substrate. Then, a contact hole is formed by removing the oxide and the HLD film and the B2O3 SOG film and the P2O5 SOG film with a plasma dry etching, and then the photo resist is removed. By diffusing a Boron and a P into the HLD film by curing the B2O3 SOG film and the P2O5 SOG film, a BPSG film(12) is formed between the HLD film and the B2O3 SOG film. And, after forming a glass layer containing Boron and P on the surface of the substrate, the glass layer is removed using a planarization method using plasma or an etchant solution(HF+DI or HF+NH4F). And, after removing the B2O3 SOG film and the P2O5 SOG film, an aluminum metal is deposited by sputtering a metal target.

Description

반도체 장치의 금속배선형성방법Metal wiring formation method of semiconductor device

제1도는 종래의 금속배선을 실시할 접촉 영역식각을 설명하기 위한 공정 단면도.1 is a cross sectional view of a process for explaining the contact area etching to perform a conventional metal wiring.

제2도는 본 발명의 금속배선을 실시할 접촉 영역식각을 설명하기 위한 공정 단면도.2 is a cross-sectional view for explaining the etching of the contact area to perform the metallization of the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 기판 2 : 게이트1 substrate 2 gate

8 : HLD막 9 : B2O3SOG막8: HLD film 9: B 2 O 3 SOG film

10 : P2O5SOG막 11 : 감광막10: P 2 O 5 SOG film 11: Photosensitive film

12 : BPSG막 13 : 유리층12 BPSG film 13: glass layer

14 : 금속14: metal

본 발명은 반도체장치의 금속배선형성방법에 관한 것으로, 특히 B2O3및 P2O5SOG(Spin On Glass)막을 이용하여 알루미늄 단차(Al Stepcoverage)를 개선할 수 있는 반도체 장치의 금속배선형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device. In particular, metal wiring formation of a semiconductor device capable of improving Al stepcoverage using B 2 O 3 and P 2 O 5 SOG (Spin On Glass) films It is about a method.

종래의 기술은 제1도 (a)와 같이 기판(규소)(1) 위에 산화막(도면 중에 도면번호 기입하지 않음)을 성장하고, 산화막 위에 게이트(2)를 패터닝(Patterning)한 후 전표면에 저압 화학증착법(LPCVD)으로 HLD(High Temperature Low Pressure Deposition)막(3)을 2000옹스트롬의 두께로 형성하고, 전표면에 APCVD법으로 440-460℃의 온도에서 SiH4는 20%, PH3는 1%, B2H61%로 하여 BPSG(Boron Phosphorus Silicate Glass)막(4)을 7000옹스트롬의 두께로 증착한다.In the prior art, as shown in FIG. 1A, an oxide film (not shown in the drawing) is grown on a substrate (silicon) 1, the gate 2 is patterned on the oxide film, and then the entire surface is patterned. a low pressure chemical vapor deposition (LPCVD) HLD (High Pressure Low temperature deposition) film 3 to form a thickness of 2000 angstroms, at a temperature of 440-460 ℃ the APCVD method on the entire surface of SiH 4 is 20%, PH 3 is A BPSG (Boron Phosphorus Silicate Glass) film 4 was deposited at a thickness of 7000 angstroms at 1% and B 2 H 6 1%.

다음, (b)와 같이 O2는 0.5리터/분, N2는 15리터/분, 온도는 900-1000℃에서 10분-20분 동안 BPSG막(4)을 평탄화하고, (c)와 같이 접촉 구멍의 기판(1) 노출영역(도면 중에 도면번호 기입하지 않음)을 제외한 표면에 감광막(5)을 형성한 후 (d)와 같이 식각용액(HF + DI와 HF + NH4F를 혼합한 용액)을 이용하여 HF 대 DI는 1 : 10, HF 대 NH4F는 1 대 20, HF + DI CH, HF + NH4F는 1 대 7 로 2-3분 동안 습식식각(Wet Etch)하고, 가스(Ar, CF4, CHF3)를 이용하여 건식식각(Dry Etch)하므로써 접촉구멍영역의 기판(1)이 드러나도록 접촉구멍영역의 상기 산화막 및 HLD막(3)과 BPSG막(4)을 제거하여 접촉구멍을 정의(Define)한다.Next, as shown in (b), O 2 is 0.5 liter / min, N 2 is 15 liter / min, and the temperature is flattened for 4 to 10 minutes to 20 minutes at 900-1000 ° C. After the photoresist film 5 was formed on the surface of the contact hole except for the exposed area of the substrate 1 (not shown in the drawing), the etching solution (HF + DI and HF + NH 4 F were mixed as shown in (d)). solution) for HF DI using a 1: 10, for NH 4 F HF is 1 to 20, HF + DI CH, HF + NH 4 F is (wet etch wet etch for 2-3 minutes to 1 - 7) The oxide film and the HLD film 3 and the BPSG film 4 in the contact hole area so that the substrate 1 in the contact hole area is exposed by dry etching using the gases Ar, CF 4 and CHF 3 . Define the contact hole by removing.

이어서, (E)와 같이 Ni는 15리터/분, O2는 0.5리터/분, 온도는 900℃~1000℃에서 30~40분 동안 BPSG막(4)을 열처리하여 평탄화하고, O2플라즈마(plasma), O3/H2SO4, H2SO4/H2O2용액을 이용하여 상기 감광막(5)을 제거하고, 이와 같은 공정에 따라 기판(1) 위에 형성된 100-200옹스트롬 정도의 두께를 갖는 산화막(6)식각용액(HF + DI 또는 HF + NH4F)을 이용하여 (f)와 같이 제거한 후 (g)와 같이 금속타겟을 스퍼터링(Sputtering)하여 전표면에 금속(Al)(7)을 증착한다.Then, as shown in (E) Ni is 15 l / min, O 2 was 0.5 liters / minute, the temperature for from 900 ℃ ~ 1000 ℃ 30 ~ 40 minutes planarization by heat-treating the BPSG film 4, and O 2 plasma ( plasma), O 3 / H 2 SO 4 , H 2 SO 4 / H 2 O 2 solution to remove the photosensitive film (5), according to the process of about 100-200 Angstrom formed on the substrate (1) After removing as shown in (f) using an etching solution (HF + DI or HF + NH 4 F) with an oxide film 6 having a thickness, sputtering the metal target as shown in (g) to the metal (Al) (7) is deposited.

그러나, 이와 같은 종래의 기술에 있어서는 SiH4, PH3, B2H6농도에 의해 보론과 인의 농도를 조절하기가 어렵고, 보론과 인의 농도 변화에 따라 BPSG막(4)의 습식시간이 변하여 건식식각시 과대한 식각이 발생하므로 플라즈마에 의해 기판의 손상(Damage)이 발생한다.However, in such a conventional technique, it is difficult to control the concentration of boron and phosphorus by the concentration of SiH 4 , PH 3 , and B 2 H 6 , and the wet time of the BPSG film 4 changes according to the change in the concentration of boron and phosphorus, resulting in a dry process. Excessive etching occurs during etching, which results in damage of the substrate by the plasma.

또한, BPSG막(4)의 습식식각시 보론과 인의 농도변화에 의한 측면 식각량의 변화 때문에 알루미늄의 단차가 악화되는 결점이 있다.In addition, the wet step of the BPSG film 4 has a drawback that the aluminum step becomes worse due to the change in the side etching amount due to the change in the concentration of boron and phosphorus.

본 발명은 이와 같은 종래의 결점을 감안하여 안출한 것으로, B2O3및 P2O5SOG막을 이용하여 금속배선을 실시한 부위의 식각 기울기를 제어하므로써 알루미늄 단차를 개선할 수 있는 반도체 장치의 금속배선형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of such conventional drawbacks, and the metal of the semiconductor device can improve the aluminum step by controlling the etch inclination of the site where metal wiring is carried out using B 2 O 3 and P 2 O 5 SOG films. The purpose is to provide a wiring forming method.

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

제2도는 본 발명의 공정 단면도로, 제2도는 (a)와 같이 기판(1) 위에 산화막을 형성하고, 산화막 위에 게이트(2)를 패터닝하는 것은 종래와 같다.2 is a cross-sectional view of the process of the present invention. FIG. 2 is an oxide film formed on the substrate 1 as shown in (a), and the gate 2 is patterned on the oxide film as in the related art.

다음, 전표면에 HLD막(8)을 9000옹스트롬 정도의 두께로 증착하고, 전표면 80℃에서 1분, 150℃에서 1분, 200℃에서 1분 동안 차례로 실시하여 1000옹스트롬 정도의 두께로 B2O SOG막(9)을 코팅(Coating)하고, 전표면에 80℃에서 1분 150℃에서 1분, 200℃에서 1분 동안 차례로 실시하여 3000옹스트롬 정도의 두께로 P2O5막(10)을 코팅한 후 (b)와 같이 기판(1) 노출영역을 제외한 표면에 감광막(11)을 형성한다.Next, the HLD film 8 was deposited on the entire surface at a thickness of about 9000 angstroms, and then sequentially performed at 80 ° C. for 1 minute, at 150 ° C. for 1 minute, and at 200 ° C. for 1 minute, to a thickness of about 1000 Angstroms. The 2 O SOG film 9 is coated, and then the entire surface is sequentially applied at 80 ° C. for 1 minute at 150 ° C. for 1 minute and at 200 ° C. for 1 minute, and the thickness of the P 2 O 5 film is about 3000 angstroms (10 ) And then the photosensitive film 11 is formed on the surface except for the exposed area of the substrate 1 as shown in (b).

이어서, (c)와 같이 가스(Ar + CF4+ CHF3)를 이용하여 플라즈마 건식식각하므로써 접촉영역의 상기 산화막, HLD막(8), B2O3SOG막(9), P2O5SOG막(10)을 제거하여 접촉구멍이 위로 부터 아래로 완만하게 좁아지는 형상이 되도록 한 후 (d)와 같이 상기 감광막(11)을 제거한다.Subsequently, the oxide film in the contact region, the HLD film 8, the B 2 O 3 SOG film 9, and P 2 O 5 by plasma dry etching using gas (Ar + CF 4 + CHF 3 ) as shown in (c). After removing the SOG film 10 so that the contact hole becomes narrow gradually from top to bottom, the photosensitive film 11 is removed as shown in (d).

또한, 열처리를 위해 N2는 15미터/분, 온도는 900-1000℃에서 30분-50분 동안 두막(9, 10)을 큐링(Curing)하여 상기 HLD막(8)으로 보론과 인이 확산하므로써 HLD막(8)과 B2O3SOG막(9) 사이에 BPSG막(12)을 형성하고, 상기 보론과 인에 의해 접촉영역의 기판(1) 표면에 보론과 인을 함유한 유리층(13)을 형성한 후 (e)와 같이 플라즈마를 이용한 평탄화법 또는 식각용액(HF + DI 또는 HF + NH4F)을 이용하여 상기 유리층(13)을 제거한다.In addition, the N 2 is 15 meters / minute and the temperature is 900-1000 ° C. for 30 minutes to 50 minutes to cure the membranes 9 and 10 for the heat treatment, and boron and phosphorus diffuse into the HLD film 8. Thus, a BPSG film 12 is formed between the HLD film 8 and the B 2 O 3 SOG film 9, and the glass layer containing boron and phosphorus on the surface of the substrate 1 in the contact region by the boron and phosphorus. After forming (13), the glass layer 13 is removed using a flattening method using an plasma or an etching solution (HF + DI or HF + NH 4 F) as shown in (e).

그리고, 상기 막(9, 10)을 제거한 후 (f)와 같이 금속타켓을 스퍼터링하여 전표면에 금속(Al)(14)을 증착한다.After removing the films 9 and 10, the metal target is sputtered as shown in (f) to deposit the metal (Al) 14 on the entire surface.

이상에서 설명한 바와 같이 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 접촉 구멍의 완만한 식각에 의해 습식식각을 생략할 수 있으므로 공정단축 및 일정한 측벽 식각량을 얻을 수 있다.First, wet etching can be omitted by gentle etching of the contact hole, so that process shortening and constant sidewall etching amount can be obtained.

둘째, 건식식각시 일정한 식각 비율로 제어되므로서 기판(1)의 손상이 없다.Second, there is no damage to the substrate 1 while being controlled at a constant etching rate during dry etching.

셋째, B2O3SOG막(9)과 P2O5SOG막(10)을 이용하여 건식식각 하므로써 일정한 보론과 인의 농도를 유지할 수 있다.Third, constant etching of boron and phosphorus may be maintained by dry etching using the B 2 O 3 SOG film 9 and the P 2 O 5 SOG film 10.

넷째, 금속타켓 스퍼터링시 접촉구멍의 개구각을 완만하게 넓혀줌으로 금속(14)의 단차가 개선되는 효과가 있다.Fourth, the step angle of the metal 14 is improved by gently widening the opening angle of the contact hole during the metal target sputtering.

Claims (7)

반도체 기판상에 HLD, 제1, 제2SOG막을 순차로 형성하는 제1단계; 상기 제2, 제1SOG막 그리고 HLD를 건식식각하여, 경사를 갖는 접촉구멍을 형성하는 제2단계; 상기 HLD와 상기 제1SOG막 사이에 BPSG층을 형성하는 제3단계; 그리고 상기 제1, 제2SOG막을 제거한 후 상기 접촉구멍 내면을 포함한 상기 기판 전면에 금속층을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.A first step of sequentially forming HLD, first and second SOG films on the semiconductor substrate; Dry etching the second and first SOG films and the HLD to form a contact hole having an inclination; Forming a BPSG layer between the HLD and the first SOG film; And forming a metal layer on the entire surface of the substrate including the inner surface of the contact hole after removing the first and second SOG films. 제1항에 있어서, 상기 제1, 제2SOG막은 각각 B2O3, P2O5로서 형성하는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.The method of claim 1, wherein the first and second SOG films are formed as B 2 O 3 and P 2 O 5 , respectively. 제2항에 있어서, 상기 제1, 제2SOG막은 각각 1000Å, 3000Å의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.The method of claim 2, wherein the first and second SOG films are formed to have a thickness of 1000 ns and 3000 ns, respectively. 제1항에 있어서, 상기 제2단계는 Ar, CF4그리고 CHF3를 포함하여 이루어지는 플라즈마 건식각방법을 이용하는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.The method of claim 1, wherein the second step comprises a plasma dry etching method including Ar, CF 4, and CHF 3 . 제1항에 있어서, 상기 제3단계는 900℃~1000℃에서 30분~50분 동안 N2분위기에서 열처리하는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.The method of claim 1, wherein the third step is a heat treatment at 900 ° C. to 1000 ° C. for 30 minutes to 50 minutes in an N 2 atmosphere. 제5항에 있어서, 상기 제3단계의 결과로 형성되는, 보론과 인을 포함하는 유리층의 식각은 플라즈마를 이용한 평탄화방법 또는 식각용액을 이용한 식각방법을 이용하는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.The metallization of the semiconductor device of claim 5, wherein the etching of the glass layer including boron and phosphorus formed as a result of the third step comprises a planarization method using plasma or an etching method using an etching solution. Formation method. 제1항에 있어서, 상기 제4단계의 상기 금속층은 Al을 이용하는 것을 특징으로 하는 반도체 장치의 금속배선형성방법.The method of claim 1, wherein the metal layer of the fourth step comprises Al.
KR1019920012905A 1992-07-20 1992-07-20 Method for forming metal interconnector of semiconductor device KR100268859B1 (en)

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