KR0166028B1 - Manufacturing methd of semiconductor device - Google Patents
Manufacturing methd of semiconductor device Download PDFInfo
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- KR0166028B1 KR0166028B1 KR1019940039091A KR19940039091A KR0166028B1 KR 0166028 B1 KR0166028 B1 KR 0166028B1 KR 1019940039091 A KR1019940039091 A KR 1019940039091A KR 19940039091 A KR19940039091 A KR 19940039091A KR 0166028 B1 KR0166028 B1 KR 0166028B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000011229 interlayer Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 24
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 장치의 제조방법을 개시한다. 개시된 본 발명은 반도체 기판 상부에 층간 절연막을 형성하는 공정과, 층간 절연막 상부에 층간 금속 절연막을 형성하는 공정과, 층간 금속 절연막 상에 사진 식각 공정에 의한 접촉창 형성용 마스크 패턴을 형성하는 공정과,마스크 패턴의 형태로 층간 금속 절연막을 식각하는 공정과, 마스크 패턴을 제거하는 공정과, 식각이 이루어진 층간 금속 절연막을 마스크로 하여, 층간 절연막을 식각하여 접촉창을 형성하는 공정과, 접촉창과 접촉되도록 전면에 금속막을 형성하는 공정과, 금속막을 층간 금속 절연막이 노출될 정도로 일괄식각하여 금속배션을 형성하는 공정을 포함한다.The present invention discloses a method of manufacturing a semiconductor device. The present invention includes the steps of forming an interlayer insulating film on the semiconductor substrate, a step of forming an interlayer metal insulating film on the interlayer insulating film, and forming a mask pattern for forming a contact window by a photolithography process on the interlayer insulating film; Etching the interlayer metal insulating film in the form of a mask pattern; removing the mask pattern; forming a contact window by etching the interlayer insulating film using the interlayer metal insulating film with etching as a mask; Forming a metal film on the entire surface of the metal film; and forming a metal basin by collectively etching the metal film to expose the interlayer metal insulating film.
Description
제1도 (a) 및 (b)는 종래의 반도체 장치의 요부 단면도.1A and 1B are cross-sectional views of principal parts of a conventional semiconductor device.
제2도는 (a) 내지 (d)는 본 발명의 일실시예에 따른 반도체 장치의 요부 단면도.2A to 2D are cross-sectional views of principal parts of a semiconductor device according to an embodiment of the present invention.
제3도 (a) 내지 (c)는 본 발명의 다른 실시예에 따른 반도체 장치의 요부 단면도.3 (a) to 3 (c) are cross-sectional views of relevant parts of a semiconductor device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 11 : 반도체 기판 3, 15 : 절연 산화막1, 11: semiconductor substrate 3, 15: insulating oxide film
4, 16 : BPSG막 17 : 층간 금속 절연막4, 16: BPSG film 17: Interlayer metal insulating film
5, 18 : 금속막5, 18: metal film
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 보다 상세하게는 금속 배선의 난반사로 인한 금속 브리지 현상 및 노치 현상을 방지할 수 있는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a metal bridge phenomenon and a notch phenomenon due to diffuse reflection of metal wiring.
종래의 반도체 소자의 제조방법에 대하여 제1도 (a) 및 (b)의 공정 단면도에 의거하여 설명한다.A conventional method for manufacturing a semiconductor device will be described based on the process sectional views of FIGS. 1A and 1B.
우선, 제1도 (a)에 있어서, 단결정의 반도체 기판(1)상에 LOCOS(LOCal Oxidation of Silicon)기술에 의하여, 반도체 소자 사이를 전기적으로 분리하기 위하여 필드 산화막(2)을 형성한다. 그 후에, 통상의 공정으로 게이트 전극(3)을 제조하고, 게이트 전극(3) 양측부에 기판(1)과 반대의 극성을 지닌 도펀트(dopant)를 도핑하여, 소오스/드레인(4)을 구성한다. 그후에, 반도체 기판(1)의 결과물 상부에 절연 산화막(5)을 형성하고, 그 상부에 BPSG막(4)을 증착한다음, 하부의 게이트 전극(3) 및 필드 산화막(2)으로 인하여 발생된 굴곡부분을 평탄화시키기 위하여 플로우(flow) 공정을 진행한다.First, in FIG. 1A, a field oxide film 2 is formed on the single crystal semiconductor substrate 1 in order to electrically separate the semiconductor elements by LOCOS (LOCal Oxidation of Silicon) technology. Thereafter, the gate electrode 3 is manufactured by a conventional process, and doped dopants having polarities opposite to those of the substrate 1 are formed at both sides of the gate electrode 3 to form the source / drain 4. do. Thereafter, an insulating oxide film 5 is formed on the resultant of the semiconductor substrate 1, and a BPSG film 4 is deposited thereon, which is generated due to the gate electrode 3 and the field oxide film 2 below. A flow process is performed to planarize the bent portion.
그 후, 금속 접촉창 형성용 마스크 패턴(도시되지 않음)을 공지된 사진 식각 공정에 의하여 제조한 다음, 소오스/드레인 영역(4)이 노출되도록, 접촉 창 형성용 마스크 패턴을 이용하여 BPSG막(6) 및 절연 산화막(5)을 식각하여, 접촉창을 형성한다. 이어서, 노출된 소오스/드레인 영역(4)과 콘택되도록, 전면에 금속막(7)을 증착한다.Thereafter, a mask pattern for forming a metal contact window (not shown) is manufactured by a known photolithography process, and then a BPSG film (using a mask pattern for forming a contact window) is exposed so that the source / drain regions 4 are exposed. 6) and the insulating oxide film 5 are etched to form a contact window. Subsequently, a metal film 7 is deposited on the entire surface to contact the exposed source / drain regions 4.
제1도 (a)에 도시된 공정 후에, 금속막(7)을 금속 배선용 마스크 패턴(도시되지 않음)을 이용하여 식각하므로써, 제1도 (b)에 보여진 바와 같은 금속 배선을 완성한다.After the process shown in Fig. 1 (a), the metal film 7 is etched using a metal wiring mask pattern (not shown), thereby completing the metal wiring as shown in Fig. 1 (b).
그러나, 본 발명자등의 실험, 검토등의 결과, 종래의 금속배선 형성 방법은 금속 증착후, 금속 배선을 형성하기 위하여, 금속 배선 상부에서 사진 식각 공정을 진행하여야 할 때, 금속의 높은 난 반사율 때문에, 식각시 금속의 잔재가 결과물 상부에 남게되어, 금속 브리지(metal bridge) 현상을 유발한다.However, as a result of experiments, studies, and the like of the present inventors, the conventional metal wiring forming method is due to the high reflectivity of the metal when a photolithography process is to be performed on the metal wiring to form the metal wiring after metal deposition. During etching, the residue of the metal remains on top of the resultant, causing a metal bridge phenomenon.
또한, 이러한 난밥사로 인하여, 금속 배선 마스크인, 포토레지스트 패턴을 형성하기 위한 노광 공정시, 패턴 측벽 부분이 일부 제거되어 노치(notch) 현상을 유발하였다.In addition, due to such an egg bob, part of the pattern sidewall portion was removed during the exposure process for forming the photoresist pattern, which is a metal wiring mask, causing a notch phenomenon.
본 발명은 상기 문제점을 해결하기 위하여 고집적 소자의 제조공정중 금속막패턴 형성시 문제가 되는 금속 브리지 및 노치등의 문제를 제거할 수 있는 반도체 장치의 제조 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of eliminating problems such as metal bridges and notches which are problematic in forming a metal film pattern during the manufacturing process of a highly integrated device in order to solve the above problems.
본 발명은 상기의 목적을 달성하기 위한 것으로, 본 발명은 반도체 기판 상부에 층간 절연막을 형성하는 공정과, 층간 절연막반드시상부에 층간 금속 절연막을 형성하는 공정과, 층간 절연막 상에 사진 식각 공정에 의한 접촉창 형성용 마스크 패턴을 형성하는 공정과, 마스크 패턴의 형태로 층간 금속 절연막을 식각하는 공정과, 마스크 패턴을 제거하는 공정과, 식각이이루어진 층간 금속 절연막을 마스크로 하여, 층간 절연막을 식각하여 접촉창을 형성하는 공정과, 접촉창과 접촉되도록 전면에 금속막을 형성하는 공정과, 금속막을 층간 금속 절연막이 노출될 정도로 일괄식각하여 금속 배선을 형성하는 공정을 포함한다.The present invention is to achieve the above object, the present invention is a process for forming an interlayer insulating film on the semiconductor substrate, the interlayer insulating film must be formed on the interlayer insulating film, and the photolithography process on the interlayer insulating film The interlayer insulating film is etched using a process of forming a contact window forming mask pattern, a step of etching the interlayer metal insulating film in the form of a mask pattern, a step of removing the mask pattern, and an etched interlayer metal insulating film as a mask. Forming a contact window; forming a metal film on the entire surface in contact with the contact window; and forming a metal wiring by collectively etching the metal film to expose the interlayer metal insulating film.
본발명은 보다 더 바람직하게는 상기 층간 금속 절연막은 노(盧, furnace)에서 형성된 TEOS막, 노에서 형성된 HTO막, PE-CVD TEOS막, PE-CVD Si-부유 산화막, SOG막, 노에서 형성된 BPSG막이거나, 상기 절연막과 층간 금속막이 일체로 되어, BPSG 후막(厚膜)인 것을 특징으로 한다.More preferably, the interlayer metal insulating film is formed from a TEOS film formed in a furnace, an HTO film formed from a furnace, a PE-CVD TEOS film, a PE-CVD Si-rich oxide film, an SOG film, or a furnace. It is a BPSG film, or the said insulating film and an interlayer metal film are integrated, and it is a BPSG thick film, It is characterized by the above-mentioned.
이하, 본 발명의 실시예를 첨부 도면에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[실시예 1]Example 1
우선, 제2도 (a)에 도시된바와 같이 반도체 기판(11) 상에 필드 산화막(12), 게이트 전극(13) 및 소오스/드레인 영역(14)을 공지의 방법으로 형성한다. 그 후에, 전면에 절연 산화막(15)을 형성하고, 절연 산화막(15)상부에 BPSG막(16)을 증착하고, 플로우(flow)시킨다. 이때, BPSG막(16)은 다층화에 의한 융기를 완화시키기 위함이다.First, as shown in FIG. 2A, a field oxide film 12, a gate electrode 13 and a source / drain region 14 are formed on a semiconductor substrate 11 by a known method. Thereafter, an insulating oxide film 15 is formed on the entire surface, and a BPSG film 16 is deposited on the insulating oxide film 15 to flow. At this time, the BPSG film 16 is for alleviating ridges due to multilayering.
그리고나서, BPSG막(16) 상부에 본 발명의 주요한 특징인 층간 금속 절연막(17: Intermetal oxide)을 형성한다. 층간 금속 절연막(17)은 노(furnace)에서 형성된 TEOS막, 노에서 형성된 HTO(high temperature oxide)막, 노에서 형성된 BPSG막, PE-CVD(plasma enhaced chemical vapor deposition) 방식의 TEOS막, PE-CVD 방식의 Si-부유(rich) 산화막 또는 SOG(spin on glass)막 중 어느 하나로 형성된다.Then, an intermetal oxide layer 17 (Intermetal oxide), which is a main feature of the present invention, is formed on the BPSG film 16. The interlayer metal insulating film 17 includes a TEOS film formed in a furnace, a high temperature oxide (HTO) film formed in a furnace, a BPSG film formed in a furnace, a TEOS film formed of a plasma-enhanced chemical vapor deposition (PE-CVD) method, and a PE- film. It is formed of either a CVD Si-rich oxide film or a spin on glass (SOG) film.
여기서, 노에서 형성되는 TEOS막은 TEOS가스, TEOS+O2가스, 또는 TEOS+O2+N2가스에 의하여 형성된다.Here, the TEOS film formed in the furnace is formed of TEOS gas, TEOS + O 2 gas, or TEOS + O 2 + N 2 gas.
또한, PE-CVD 방식에 의하여 형성되는 TEOS막은 TEOS+O2가스, 또는 TEOS+O2_N2가스에 의하여 형성된다.In addition, the TEOS film formed by PE-CVD is formed by TEOS + O 2 gas or TEOS + O 2 _N 2 gas.
또한, PE-CVD 방식에 의하여 형성는 Si-부유 산화막은 SiH4+N2O 가스 또는 SiH4+N2O+N2가스에 의하여 형성될 수 있으며, 노에서 이용되는 HTO막은 SiH4+N2O 가스 또는 SiH4+N2O+N2가스에 의하여 형성된다.In addition, the Si-rich oxide film formed by PE-CVD may be formed by SiH 4 + N 2 O gas or SiH 4 + N 2 O + N 2 gas, and the HTO film used in the furnace is SiH 4 + N 2. It is formed by O gas or SiH 4 + N 2 O + N 2 gas.
노에서 형성되는 BPSG막은 SiH4+O2+PH3+B2H6+N2가스에 의하여 형성된다.The BPSG film formed in the furnace is formed by SiH 4 + O 2 + PH 3 + B 2 H 6 + N 2 gas.
그 후, 제2도 (b)에 도시된 바와 같이, 층간 금속 절연막(17) 상에 접촉창 형성용 포토레지스트 패턴(도시되지 않음)을 공지희 방식으로 형성한다음, 이 포토레지스트 패턴의 형태로 층간 금속 절연막(17)을 식각한다. 그후, 접촉창 형성용 포토레지스트 패턴을 공지의 방식으로 제거한다. 여기서, 상기 식각이 이루어진 층간 금속 절연막(17)은 실제적인 접촉창 형성용 마스크의 역할을 하게 된다.Then, as shown in FIG. 2 (b), a photoresist pattern (not shown) for forming a contact window is formed on the interlayer metal insulating film 17 in a known manner, and then in the form of this photoresist pattern. The interlayer metal insulating layer 17 is etched. Thereafter, the photoresist pattern for forming the contact window is removed in a known manner. Here, the etched interlayer metal insulating layer 17 serves as a mask for forming an actual contact window.
그리고나서, 층간 금속 절연막(17)을 마스크로 하여, 노출된 BPSG막(16) 및 절연 산화막(15)을 식각하여 접촉창을 형성한다. 그 후, 결과물 전면에 금속막(18)을 형성하다. (제2도 (c) 참조)Then, using the interlayer metal insulating film 17 as a mask, the exposed BPSG film 16 and the insulating oxide film 15 are etched to form a contact window. Thereafter, the metal film 18 is formed on the entire surface of the resultant product. (See Figure 2 (c))
그 다음에, 제2도 (d)에 도시된 바와 같이, 금속막(18)을 층간 금속 절연막(17)이 노출될때까지, 일괄 식각(blanket etch)하여, 접촉창내에 금속막(18)이 매립되는 형태의 금속 배선(19)을 형성한다. 이와같이 하면, 금속막(18) 상부에 금속 배선(19)을 형성하기 위한 포토레지스트 패턴 형성 공정이 생략되므로써, 금속 브리지 현상 및 노치 현상이 발생되지 않는다. 더구나, 금속 배선(19)의 접촉창내에 매립되므로, 바람직한 평탄화도 이룰 수 있다.Next, as shown in FIG. 2 (d), the metal film 18 is etched in a blanket until the interlayer metal insulating film 17 is exposed, so that the metal film 18 is formed in the contact window. A metal wiring 19 is formed to be embedded. In this way, the photoresist pattern forming process for forming the metal wiring 19 over the metal film 18 is omitted, so that metal bridge phenomenon and notch phenomenon do not occur. Moreover, since it is buried in the contact window of the metal wiring 19, preferable planarization can also be achieved.
[실시예 2]Example 2
우선, 제3도 (a)에 도시된 바와 같이 반도체 기판(11)상에 필드 산화막(12), 게이트 전극(13) 및 소오스/드레인 영역(14)을 순차적으로 형성한다. 그 후에, 전면에 절연 산화막(15)을 형성하고, 절연 산화막(15) 상부에 BPSG막(16A)을 증착한 후 플로우(flow)시킨다. BPSG막(16A)을 이용하는 것은 반도체 장치의 특성에 영향을 미치는 나트륨(Na)이온을 포획하고 다층화에 의한 융기를 완화시키기 위함이다. 여기서는 BPSG막(16A)을 실시예 1에서보다 두껍게 증착하여, 실시예 1에서의 형성한 층간 금속 절연막(17)을 생략하면서 토플로지를 완호시킬 수 있는 것을 특징으로 한다. (제3도 (a) 참조)First, as shown in FIG. 3A, the field oxide film 12, the gate electrode 13, and the source / drain regions 14 are sequentially formed on the semiconductor substrate 11. Thereafter, an insulating oxide film 15 is formed on the entire surface, and a BPSG film 16A is deposited on the insulating oxide film 15 and then flowed. The use of the BPSG film 16A is for trapping sodium (Na) ions affecting the characteristics of the semiconductor device and alleviating the ridges due to the multilayering. In this case, the BPSG film 16A is deposited thicker than in the first embodiment, and the topologies can be completed while omitting the interlayer metal insulating film 17 formed in the first embodiment. (See Figure 3 (a))
그 후, 상기 두껍게 형성된 BPSG막(16A)상에 접촉창 형성용 포토레지스트 패턴(도시되지 않음)을 공지의 방식으로 형성하고, 이 포토레지스트 패턴을 이용하여 BPSG막(16A)을 식각한다. 그후, 포토레지스트 패턴을 공지의 방식으로 제거한다. 이로써 BPSG막(16A)이 후속 공정에서 금속 배선 마스크로서 역할을 할 수 있는 구조를 이루게 된다.(제3도 (b) 참조)Thereafter, a photoresist pattern (not shown) for forming a contact window is formed on the thickly formed BPSG film 16A in a known manner, and the BPSG film 16A is etched using the photoresist pattern. The photoresist pattern is then removed in a known manner. This results in a structure in which the BPSG film 16A can serve as a metal wiring mask in a subsequent step (see FIG. 3 (b)).
그리고 나서, 식각이 이루어진 BPSG막(16A)을 마스크로 이용하여, 노출된 절연 산화막(15)을 식각하여 접촉창을 형성한다. 그 후에 전면에 금속막을 증착한다음, 상술한 일괄 식각을 이용하여 접촉창내에 매립된 형태의 금속 배선(19)을 형성한다. (제3도 (c) 참조)Then, using the etched BPSG film 16A as a mask, the exposed insulating oxide film 15 is etched to form a contact window. Thereafter, a metal film is deposited on the entire surface, and then the metal wiring 19 embedded in the contact window is formed using the above described batch etching. (See Figure 3 (c))
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 금속막 상부에서의 마스크 형성 공정을 배제하므로써, 마스크 패턴 형성시, 또는 금속 배선 형성시 발생되는 금속막의 브리지 및 노치 현상을 방지하게 된다.As described in detail above, according to the present invention, by eliminating the mask formation process on the upper portion of the metal film, the bridge and notch phenomenon of the metal film generated during mask pattern formation or metal wiring formation is prevented.
따라서, 후속 공정을 진행하는데, 용이하다.Thus, it is easy to proceed with the subsequent process.
더욱이, 상기와 같이 일괄 식각 공정에 의하여 금속 배선이 접촉창내에 매립되어 있으므로, 반도체 기판 결과물이 평탄해진다.Furthermore, since the metal wiring is embedded in the contact window by the batch etching process as described above, the semiconductor substrate resultant becomes flat.
Claims (7)
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