KR0184939B1 - Bonding pad formation method of semiconductor device - Google Patents
Bonding pad formation method of semiconductor device Download PDFInfo
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- KR0184939B1 KR0184939B1 KR1019950041460A KR19950041460A KR0184939B1 KR 0184939 B1 KR0184939 B1 KR 0184939B1 KR 1019950041460 A KR1019950041460 A KR 1019950041460A KR 19950041460 A KR19950041460 A KR 19950041460A KR 0184939 B1 KR0184939 B1 KR 0184939B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
Abstract
본 발명은 반도체 소자의 본딩패드 형성방법에 관한 것으로, 본딩패드를 노출시키기 위한 식각공정시 반사방지막의 과도식각으로 인해 발생되는 언더컷을 방지하기 위하여 실리콘 이온 주입을 하므로써 본딩패드 표면에서 발생되는 부식을 방지하며 소자의 소자의 전기적 특성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bonding pad of a semiconductor device. It can prevent and improve the electrical characteristics of the device of the device.
Description
제1a 내지 1c도는 종래 반도체 소자의 본딩패드 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a bonding pad of a conventional semiconductor device.
제2a 내지 2d도는 본 발명의 제 1실시예를 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining the first embodiment of the present invention.
제3a 내지 3d도는 본 발명의 제 2실시예를 설명하기 위한 소자의 단면도.3A to 3D are cross-sectional views of devices for explaining the second embodiment of the present invention.
* 도면의 주요부분에 대한 기호설명* Symbol description for main parts of the drawing
1, 11 및 21 : 실리콘기판 2 ,12 및 22 : 절연막1, 11 and 21: silicon substrates 2, 12 and 22: insulating film
3, 13 및 23 : 합금막 4, 14 및 24 : 반사방지막3, 13 and 23: alloy film 4, 14 and 24: antireflection film
5, 15 및 25 : 산화막 6, 16 및 26 : 질화막5, 15 and 25: oxide film 6, 16 and 26: nitride film
17, 27 : 본딩패드 18 및 28 : 감광막17, 27: bonding pads 18 and 28: photosensitive film
본 발명은 반도체 소자의 본딩패드 형성방법에 관한 것으로서, 특히 본딩패드를 노출시키기 위한 식각공정시 실리콘 이온주입을 이용하여 식각비를 조절하므로써 반사방지막의 과도식각으로 인해 발생되는 언더컷을 방지할 수 있는 반도체 소자의 본딩패드 형성방법에 관한 것이다.The present invention relates to a method for forming a bonding pad of a semiconductor device, and in particular, by controlling the etching ratio by using silicon ion implantation during the etching process for exposing the bonding pad, it is possible to prevent undercuts caused by excessive etching of the anti-reflection film. A method for forming a bonding pad of a semiconductor device.
일반적으로 반도체 소자의 본딩패드는 외부와의 접속을 위한 리드 프레임과 실리콘기판상에 형성된 소자를 접속시키기 워해 형성한다. 그러면 종래 반도체 소자의 본딩패드를 형성하기 위한 본딩패드 형성방법을 제 1a 내지 1c 도를 통해 설명하면 다음과 같다.In general, a bonding pad of a semiconductor device is formed by connecting a device formed on a silicon substrate with a lead frame for connection with the outside. Next, a method of forming a bonding pad for forming a bonding pad of a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.
제 1a 내지 1c 도는 종래 반도체 소자의 본딩패드 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method of forming a bonding pad of a conventional semiconductor device.
제 1a도는 소자제조 공정을 거친 실리콘기판(1)상에 절연막(2)을 형성한 후 상기 절연막(2)상에 합금막(3) 및 반사방지막(4)을 순차적으로 형성하고 상기 반사방지막(4) 및 합금막(3)을 순차적으로 패터닝한 상태의 단면도이다.FIG. 1A shows an insulating film 2 formed on a silicon substrate 1 which has been subjected to a device fabrication process, followed by sequentially forming an alloy film 3 and an antireflection film 4 on the insulating film 2. 4) and sectional view of the alloy film 3 in the patterned state sequentially.
제 1b도는 전체 상부면에 산화막(5) 및 질화막(6)을 순차적으로 행성한 상태의 단면도이고, 제 1c 도는 상기 질화막(6), 산화막(5) 및 반사방지막(4)을 순차적으로 패터닝하여 상기 합금막(3)의 표면을 소정부분 노출시키므로써 본딩패드(7)가 형성된 상태의 단면도이다. 그런데 이때 식각비차이로 인하여 상기 반사방지막(4)이 과도식각되기 때문에 상기 패터닝된 산화막(5) 하부에 언더컷(A부분)이 발생된다. 그러므로 계속하여 본딩공정이 이루어 지는 경우 상기 언더컷(A부분)된 부분에 수증기를 포함한 공기가 존재하기 때문에 상기 언더컷(A부분)에 의해 노출된 부위의 합금막(3)의 표면이 부식되어 소자의 불량이 유발된다.FIG. 1B is a cross-sectional view of a state in which the oxide film 5 and the nitride film 6 are sequentially planetized on the entire upper surface thereof, and FIG. 1C is a patterned pattern of the nitride film 6, the oxide film 5, and the antireflection film sequentially. It is sectional drawing of the state in which the bonding pad 7 was formed by exposing the surface of the said alloy film 3 to the predetermined part. However, at this time, because the anti-reflection film 4 is excessively etched due to the etching difference, an undercut (part A) is generated under the patterned oxide film 5. Therefore, when the bonding process is continuously performed, the surface of the alloy film 3 of the portion exposed by the undercut (A part) is corroded because the air containing water vapor exists in the undercut (part A). Defects are caused.
따라서 본 발명은 본딩패드를 노출시키기 위한 식각공정시 실리콘 이온주입을 이용하여 식각비를 조절하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 본딩패드 형성방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a bonding pad of a semiconductor device which can solve the above disadvantages by controlling the etching ratio by using silicon ion implantation during an etching process for exposing the bonding pad.
상기 목적을 달성하기 위한 본 발명은 소자제조 공정을 거친 실리콘 기판상에 절연막을 형성한 후 상기 절연막상에 합금막 및 반사방지막을 순차적으로 형성하고 상기 반사방지막 및 합금막을 순차적으로 패터닝하는 단계와, 상기 단계로부터 전체 상부면에 산화막 및 질화막을 순차적으로 형성하는 단계와, 상기 단계로부터 전체 상부면에 감광막을 도포한 후 경화공정을 실시하는 단계와, 상기 단계로부터 본딩패드가 형성된 부분의 상기 질화막이 노출되도록 상기 감광막을 패터닝하고, 상기 패터닝된 감광막을 마스크로 이용하여 상기 노출된 질화막 및 상기 노출된 질화막 하부의 산화막 및 반사방지막에 실리콘이온을 주입하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용하여 상기 이온주입된 질화막, 산화막 및 반사방지막을 순차적으로 비등방성 식각하여 상기 합금막의 표면을 소정부분 노출시키므로써 본딩패드가 형성되도록 하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a step of forming an insulating film on the silicon substrate subjected to the device manufacturing process and then sequentially forming an alloy film and an antireflection film on the insulating film and patterning the antireflection film and the alloy film sequentially; Sequentially forming an oxide film and a nitride film on the entire upper surface from the step; applying a photosensitive film to the entire upper surface from the step; performing a curing process; and the nitride film of the portion where the bonding pad is formed from the step. Patterning the photoresist film to be exposed, and implanting silicon ions into the exposed nitride film and the oxide film and the anti-reflection film under the exposed nitride film using the patterned photoresist as a mask, and masking the patterned photoresist film from the step. By using the ion implanted nitride film, oxide film and antireflection By the anisotropic etching in order to write because the predetermined portion exposed to the alloy layer surface is characterized in that comprising the steps of: to form a bonding pad.
또한 본 발명에 의하면 소자제조 공정을 거친 실리콘기판상에 절연막을 형성한 후 상기 절연막상에 합금막 및 반사방지막을 순차적으로 형성하고 상기 반사방지막 및 합금막을 순차적으로 패터닝하는 단계와, 상기 단계로부터 전체 상부면에 산화막 및 질화막을 순차적으로 형성하는 단계와, 상기 단계로부터 전체 상부면에 감광막을 도포한 후 정화공정을 실시하는 단계와, 상기 단계로부터 본딩패드가 형성됨 부분의 상기 질화막이 노출되도록 상기 감광막을 패터닝하고, 상기 패터닝된 감광막을 마스크로 이용하여 상기 산화막의 수정부분이 노출되도록 소정가스 분위기하에서 식각공정으로 상기 질화막을 제거하는 단계와, 상기 단계로부터 상기 감광막을 마스크로 이용하여 산화막 및 반사방지막에 실리콘 이온을 주입하는 단계와, 상기 단계로부더 상기 패터닝된 감광막을 마스크로 이용하여 상기 이온주입된 산화막 및 반사방지막을 순차적으로 비등방성 식각하여 상기 합금막의 표면을 소정부분 노출시키므로써 본딩패드가 형성되도록 하는 단계로 이루는 것을 특징으로 한다.In addition, according to the present invention, after forming an insulating film on the silicon substrate subjected to the device manufacturing process, sequentially forming an alloy film and an anti-reflection film on the insulating film, and sequentially patterning the anti-reflection film and the alloy film, and from the above step Sequentially forming an oxide film and a nitride film on the upper surface, applying a photoresist film to the entire upper surface from the step, and then performing a purification process, and exposing the nitride film in a portion where the bonding pad is formed from the step. Patterning and removing the nitride film by an etching process under a predetermined gas atmosphere using the patterned photosensitive film as a mask to expose the quartz portion of the oxide film; and from the step, using the photosensitive film as a mask, an oxide film and an anti-reflection film Implanting silicon ions into the Further to the patterned photosensitive film characterized in that by using as a mask a step of forming so that the ions to the implanted oxide layer and the anti-reflection film anisotropic etching sequentially written because a predetermined portion exposed to the alloy layer surface to form a bonding pad.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2a 내지 2d 도는 본 발명의 제 1실시예를 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for explaining the first embodiment of the present invention.
제 2a 도는 소자제조 공정을 거친 실리콘기판(11)상에 절연막(12)을 형성한 후 상기 절연막(12)상에 합금막(13) 및 반사방지막(14)을 순차적으로 형성하고 상기 반사방지막(14) 및 합금막(13)을 순차적으로 패터닝한 상태의 단면도로서, 상기 합금막(13)은 알루미늄(Al) 및 0.3 내지 0.7%의 구리(cu)로 이루어지며, 8000내지 12000Å의 두께로 중착된다. 그리고 상기 반사방지막(14)은 티타늄 나이트라이드(TiN)를 200 내지 500Å의 두께로 증착하여 형성한다.2A or after the insulating film 12 is formed on the silicon substrate 11 subjected to the device fabrication process, the alloy film 13 and the anti-reflection film 14 are sequentially formed on the insulating film 12, and the anti-reflection film ( 14) and a cross-sectional view of the alloy film 13 sequentially patterned, wherein the alloy film 13 is made of aluminum (Al) and 0.3 to 0.7% of copper (cu), and has a thickness of 8000 to 12000 kPa. do. The anti-reflection film 14 is formed by depositing titanium nitride (TiN) to a thickness of 200 to 500 Å.
제 2b도는 전체 상부면에 산화막(l5) 및 질화막(16)을 순차적으로 형성한 상태의 단면도로서, 상기 산화막(15)은 플라즈마 보조산화막이며 2000 내지 4000Å의 두께로 형성된다. 그리고 상기 질화막(16)은 플라즈마 보조 질화막이며, 4000 내지 6000Å의 두께로 형성된다.FIG. 2B is a cross-sectional view of the oxide film l5 and the nitride film 16 sequentially formed on the entire upper surface thereof. The oxide film 15 is a plasma auxiliary oxide film and is formed to have a thickness of 2000 to 4000 kPa. The nitride film 16 is a plasma assisted nitride film and is formed to a thickness of 4000 to 6000 GPa.
제 2C 도는 전체 상부면에서 감광막(18)을 2.8 내지 3.2㎛의 두께로 도포한 후 경화공정으로 100 내지 150℃의 온도로 20 내지 40분간 경화(베이크)시킨다. 이후 본딩패드가 형성된 부분의 상기 질화막(16)이 노출되도록 상기 감광막(18)을 패터닝하고, 상기 패터닝된 감광막(18)을 마스크로 이용하여 상기 노출된 질화막(16) 및 그 하부의 산화막(15) 및 반사방지막(14)에 실리콘(Si)이온을 주입한 상태의 단면도로서, 상기 실리콘(Si) 이온주입에 의해 상기 반사방지막(14)은 비정질화 된다. 상기 실리콘 주입시 이온주입 에너지는 200 내지 300KeV이며, 이온주입량은 1 × 1014내지 1 × 1017원자/cm2가 되도록 한다.2C is a photosensitive film 18 is applied to the entire upper surface in a thickness of 2.8 to 3.2㎛ and then cured (baked) for 20 to 40 minutes at a temperature of 100 to 150 ℃ by the curing process. Afterwards, the photosensitive film 18 is patterned to expose the nitride film 16 of the portion where the bonding pad is formed, and the exposed nitride film 16 and the oxide film 15 below the patterned photosensitive film 18 are used as a mask. ) And the anti-reflection film 14 is a cross-sectional view in which silicon (Si) ions are implanted, and the anti-reflection film 14 is amorphous by the silicon (Si) ion implantation. In the silicon implantation, the ion implantation energy is 200 to 300 KeV, and the ion implantation amount is 1 × 10 14 to 1 × 10 17 atoms / cm 2 .
제 2d 도는 상기 패터닝된 감광막(18)을 마스크로 이용하여 상기 이온주입된 질화막(16), 산화막(15) 및 반사방지막(14)을 순차적으로 비등방성 식각하여 상기 합금막(13)의 표면을 소정부분 노출시키므로써 본딩패드(17)가 형성된 상태의 단면도이다.2D or anisotropically etch the ion implanted nitride film 16, oxide film 15 and anti-reflection film 14 using the patterned photosensitive film 18 as a mask to etch the surface of the alloy film 13. It is sectional drawing of the state in which the bonding pad 17 was formed by exposing predetermined part.
상기 식각공정에 이용되는 가스는 CF4, CHF3, Ar 및 O2가스이며, 상기 CF4가스량은 20 내지 100SCCM이고, CHF3가스량은 : 20 내지 50SCCM이고, Ar가스량은 300 내지 500SCCM이며, O2가스량은 10 내지 20SCCM이다. 그리고 상기 식각공정에 사용되는 압력은 1.0 내지 1.5Torr이고, 전력은 300 내지 600W이다. 여기서 상기 실리콘(Si) 이온의 주입에 의해 상기 감광막(18)은 4000 내지 4500Å/min의 식각비를 가지게 되고, 상기 산화막(15)은 7000 내지 7500Å/min의 식각비를 가지게되며, 상기 질화막(16)은 10000 내지 11000Å/min의 식각비를 갖게된다. 그러므로 상기 반사방지막(14)의 과도식각이 방지되어 언더컷이 발생되지 않는다.Gases used in the etching process are CF 4 , CHF 3 , Ar and O 2 gas, the CF 4 gas amount is 20 to 100SCCM, the CHF 3 gas amount is: 20 to 50SCCM, the Ar gas amount is 300 to 500SCCM, O 2 gas amount is 10-20SCCM. And the pressure used in the etching process is 1.0 to 1.5 Torr, the power is 300 to 600W. Here, the photosensitive film 18 has an etching ratio of 4000 to 4500 kW / min by the implantation of silicon (Si) ions, and the oxide film 15 has an etching ratio of 7000 to 7500 kW / min, and the nitride film ( 16) has an etching ratio of 10000 to 11000 mW / min. Therefore, the over-etching of the anti-reflection film 14 is prevented so that no undercut is generated.
이하, 첨부된 도면을 참조하여 본 발명의 다른 실시예를 상세히 설명 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described another embodiment of the present invention;
제 3a 내지 3d 도는 본 발명의 제 2실시예를 설명하기 위한 소자의 단면도이다.3A to 3D are cross-sectional views of devices for explaining the second embodiment of the present invention.
제 3a 도는 소자제조 공정을 거친 실리콘기판(21)상에 절연막(22)을 형성한 후 상기 절연막(22)상에 합금막(23) 및 반사방지막(24)을 순차적으로 형성하고 상기 반사방지막(24) 및 합금막(23)을 순차적으로 패터닝한 상태의 단면도로서, 상기 합금막(23)은 알루미늄(Al) 및 0.3 내지 0.7%의 구리(Cu)로 이루어지며, 8000 내지 12000Å의 두께로 증착된다. 그리고 상기 반사방지막(24)은 티타늄 나이트라이드(TiN)를 200 내지 500Å의 두깨로 증착하여 형성한다.After the insulating film 22 is formed on the silicon substrate 21 which has undergone the process of manufacturing a device 3a or 3b, the alloy film 23 and the anti-reflection film 24 are sequentially formed on the insulating film 22, and the anti-reflection film ( 24) and a cross-sectional view of the alloy film 23 sequentially patterned, wherein the alloy film 23 is made of aluminum (Al) and 0.3 to 0.7% copper (Cu), and is deposited to a thickness of 8000 to 12000 kPa. do. The anti-reflection film 24 is formed by depositing titanium nitride (TiN) with a thickness of 200 to 500 kPa.
제 3b도는 전체 상부면에 산화막(25) 및 질화막(26)을 순차적으로 형성한 상태의 단면도로서, 상기 산화막(25)은 플라즈마 보조산화막이며, 2000 내지 4000Å의 두께로 형성된다. 그리고 상기 질화막(26)은 플라즈마 보조 질화막이며 4000내지 6000Å의 두께로 형성된다.FIG. 3B is a cross-sectional view of the oxide film 25 and the nitride film 26 formed sequentially on the entire upper surface. The oxide film 25 is a plasma auxiliary oxide film and is formed to have a thickness of 2000 to 4000 kPa. The nitride film 26 is a plasma assisted nitride film and is formed to a thickness of 4000 to 6000 kPa.
제 3C 도는 전체 상부면에 감광막(28)을 2.8 내지 3.2μm의 두께로 도포한 후 정화공정으로 100 내지 150℃의 온도로 20 내지 40분간 경화(베이크)시킨다. 이후 본딩패드가 형성됨 부분의 상기 질화막(26)이 노출되도록 상기 감광막(18)을 패터닝하고, 상기 패터닝된 감광막(18)을 마스크로 이용하여 상기 산화막(25)의 소정부분이 노출되도록 SF6및 He가스분위기하에서 식각공정으로 상기 질화막(26)을 제거한다. 이후 상기 감광막(28)을 마스크로 이용하여 산화막(25) 및 반사방지막(24)에 실리콘(Si) 이온을 주입한다. 이때 상기 실리콘(Si) 이온 주입에 의해 상기 반사방지막(14)은 비정질화 된다. 상기 실리콘(Si)이온 주입시 이온 주입 에너지는 150 내지 250KeV이며, 이온주입량은 1 × 1014내지 1 × 1017원자/cm2가 되도록 한다.3C is a photosensitive film 28 is applied to the entire upper surface in a thickness of 2.8 to 3.2μm and then cured (baked) for 20 to 40 minutes at a temperature of 100 to 150 ℃ by the purification process. Since SF 6, and such that the bonding pad is patterning the photoresist layer 18 so that the nitride film 26 is exposed in the formed part, and the predetermined portion of the oxide film 25 exposed by the patterned photoresist 18 as a mask. The nitride layer 26 is removed by an etching process under a He gas atmosphere. Thereafter, silicon (Si) ions are implanted into the oxide film 25 and the anti-reflection film 24 using the photosensitive film 28 as a mask. At this time, the anti-reflection film 14 is amorphous by the silicon (Si) ion implantation. In the silicon (Si) ion implantation, the ion implantation energy is 150 to 250 KeV, and the ion implantation amount is 1 × 10 14 to 1 × 10 17 atoms / cm 2 .
제 3d 도는 상기 패터닝된 감광막(28)을 마스크로 이용하여 상기 이온주입된 산화막(25) 및 반사방지막(24)을 순차적으로 비등방성 식각하여 상기 합금막(13)의 표면을 소정부분 노출시키므로써 본딩패드(27)가 형성된 상태의 단면도이다. 상기 식각공정에 이용되는 가스는 CF4, CHF3, Ar 및 O2가스이며, 상기 CF4가스량은 20 내지 100SCCM이고, CHF3가스량은 20 내지 50SCCM이고, Ar가스량은 300 내지 500SCCM이며, O2가스량은 10 내지 20SCCM이다. 그리고 상기 식각공정에 사용되는 압력은 1.0 내지 1.5Torr이고, 전력은 300 내지 600W이다. 그러므로 상기 반사방지막(14)의 과도식각이 방지되어 언더컷이 발생되지 않는다.3D or by anisotropically etching the ion-implanted oxide film 25 and the anti-reflection film 24 using the patterned photosensitive film 28 as a mask to expose a portion of the surface of the alloy film 13 by It is sectional drawing of the state in which the bonding pad 27 was formed. Gases used in the etching process are CF 4 , CHF 3 , Ar and O 2 gas, the amount of CF 4 gas is 20 to 100SCCM, the amount of CHF 3 is 20 to 50SCCM, the amount of Ar gas is 300 to 500SCCM, O 2 The amount of gas is 10-20SCCM. And the pressure used in the etching process is 1.0 to 1.5 Torr, the power is 300 to 600W. Therefore, the over-etching of the anti-reflection film 14 is prevented so that no undercut is generated.
상술한 바와같이 본 발명에 의하면 본딩패드를 노출시키기 위한 식각 공정시 실리콘 이온 주입을 이용하여 식각비를 조절하므로써 반사방지막의 과도식각에 의한 본딩패드 표면에서 발성되는 부식을 방지하여 소자의 전기적 특성을 향상시킬 수 있는 탁월한 효과가 있는 것이다.As described above, according to the present invention, by controlling the etching ratio by using silicon ion implantation during the etching process for exposing the bonding pad, the electrical characteristics of the device are prevented by preventing corrosion caused by the excessive surface etching of the antireflection film. There is an excellent effect that can be improved.
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