JP2873759B2 - Pretreatment method for wet etching of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improved method for a pre-process in a wet etching technique using a photoresist film as a mask.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor device, various methods are required for patterning an insulating film and a metal film formed on a semiconductor substrate into a desired shape and for forming a contact hole in an interlayer insulating film for forming a multilayer wiring. Is used.

For example, in order to obtain a good contact hole shape, wet etching is used in an initial opening stage in order to form an appropriate taper angle around the opening by utilizing its isotropic property.

FIG. 3 is a longitudinal sectional view of the semiconductor substrate for explaining the process. In FIG. 3A, the lower wiring 2, the interlayer insulating film 3 and the photo-resistor provided on the semiconductor substrate 1 are shown. A resist film 4 patterned by a lithography process is formed.

Using the resist film 4 as a mask, for example, wet etching is performed using an HF-NH ₄ F aqueous solution to form an initial opening upper portion 5 shown in FIG. Next, as shown in FIG. 3C, reactive ion etching (C
The lower portion 6 of the opening is formed by dry etching using HF ₃ -O ₂ gas), and the resist film 4 is removed in FIG. 3D to form a contact hole 7 in the interlayer insulating film 3.

However, in the conventional wet etching,
The interlayer insulating film, especially the BPSG film and the PSG film, depending on the deposition conditions of the film, have poor adhesion to the resist, so that the etching solution permeates the bonding surface with the resist, and as a result, as shown in FIG. An undercut is formed below the resist film 4, and the upper portion of the opening becomes unnecessarily large, so that not only a good taper angle is not obtained, but also the design rule for miniaturization cannot be met.

[0007] In addition, the poor adhesion causes a problem that the developing solution permeates between the interlayer insulating film and the resist film even during the development of the resist film in the photolithography process, thereby causing the peeling of the resist. .

Conventionally, the following measures have been taken in order to improve the adhesion between the thin film and the thin film by wet etching using the resist film as a mask.

(1) A method of performing plasma treatment with a gas such as nitrogen before wet etching (Japanese Patent Laid-Open No. 63-1)
No. 69030).

(2) A method of performing a treatment (reach treatment) with hot sulfuric acid or hot sulfuric acid / hydrogen peroxide before the resist film coating step (see JP-A-3-136317).

(3) A method of treating a substrate with a halogenated silane or an alkylated silazane before the resist film coating step (RO Lussow, AA Bergh: J. Electrochem. Soc.,
112).

(4) A method of modifying the resist itself to improve the adhesion to various thin films.

However, (1) is affected by the atmosphere and the time of exposure from the processing to the resist coating step, and (2) is the adhesion of PSG and BPSG containing high-concentration impurities to the resist. Although the properties are improved to some extent, it is necessary to wash with water after the treatment, and it is necessary to consider the effects of this contamination in the water.In (3), the optimum conditions for the treatment and its effects are determined by the surface condition of the thin film material. However, it lacks stability.In (4), in addition to responding to the trend of miniaturization, the range of resists that can be further selected from the conditions for satisfying this compatibility is extremely limited, and it is not a practical method. I can't say.

[0014]

In view of such circumstances, the present invention provides a method for removing a resist by a developer in a photolithography process and performing wet etching without using the conventional methods (1) to (4). It is an object of the present invention to provide a novel wet etching pre-treatment method for a semiconductor device in which the occurrence of undercut is prevented.

[0015]

According to the present invention, a photoresist film is formed on a thin film formed on a semiconductor substrate, the photoresist film is formed into a desired pattern, and the photoresist film is used as a mask. In the etching method, a step of forming an oxide film on the thin film by a plasma vapor deposition method using an oxidation reaction of monosilane (SiH ₄ ) is added before the step of applying a photoresist. .

In the present invention, the thin film to which the photoresist film is applied is a BPSG film used as an interlayer insulating film,
A thin film that can be wet-etched using a patterned resist film as a mask, such as a PSG film and P-TEOS (oxide film by thermal decomposition of tetraethoxysilane), as well as other interlayer insulating films for forming multiple wirings, may be used. The photoresist and etching solution used are not limited, and those commonly used can be used.

In the wet etching process, both the thin film and the plasma CVD oxide film of the present invention formed on the thin film can be etched, and if this oxide film is formed sufficiently thick as required for the etching depth. In this case, the oxide film can be etched only by the adhesion layer (adhe-si
on layer), in the latter, taper etch
Functions as a layer.

The oxide film used in the present invention is monosilane
(SiH_Four Plasma C formed by the oxidation reaction of
VD oxide film can be used, and SiH_Four -O  System, S
iH_Four-N_Two O-based and SiH_Four -H_Two Well-known such as O-based
Can be used, but SiH_Four −
N_Two An O-based plasma CVD oxide film is particularly desirable.
The film thickness may usually be about 300 ° or more.

[0019]

According to the above-mentioned structure, since monosilane oxide having strong adhesion to the resist film serving as a mask during wet etching is deposited by the plasma CVD method, the developing solution and the etching solution in the photolithography process are formed. Is prevented from entering the interlayer insulating film. Therefore, this plasma CVD oxide film functions as an adhesion layer between the photoresist film and the thin film when the thin film below the oxide film is wet-etched, and as a taper etch layer when only this oxide film is wet-etched. I do.

[0020]

An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing a cross-sectional shape of a wet-etched portion after performing the following processing. That is, a BPSG film 11 is deposited as an interlayer insulating film on the lower wiring 10 of the semiconductor substrate to a thickness of 4,000 Å, and an SiH ₄ —N ₂ O
A system oxide film 13 is deposited by plasma CVD to a thickness of 2,000 mm under the following conditions.

(Condition 1) Reaction gas: SiH ₄ / H ₂ O = 240 /
4200 sccm Pressure: 2 Torr Temperature: 400 ° C. Power: 800 W Carrier gas: N 2, 2800 sccm Next, a positive resist 12 was spin-coated, and the resist was patterned by a normal photolithography process to form an opening 14 for a contact hole. Later, HF
The -NH ₄ F solution is obtained by wet etching.

As is known from FIG. 1, plasma CVD
The oxide film has a good taper angle with a radius at the periphery below the opening by ideal isotropic etching, and is known to be effective as a taper etch layer.

FIG. 2 shows another embodiment of the present invention, which is processed under the same conditions as in the first embodiment except that the thickness of the plasma CVD oxide film 13 is set to 500 mm. In this embodiment, in addition to the oxide film 13,
Although the SG film is also wet-etched, the oxide film functions as an adhesion layer for each of the upper and lower layers, so that no etching liquid penetrates into the side and good etching is performed.

Next, a comparative example (FIGS. 5 and 6) corresponding to this embodiment will be described in order to clarify the operation of the present invention.

FIG. 5 is a similar sectional view obtained under the same conditions as in Example 1 except that the oxide film 13 in Example 1 is not provided. In this example, it can be seen that the etching progresses in the lateral direction and the undercut 15 is formed large.

FIG. 6 shows an oxide film 1 according to the second embodiment.
3 in place of tetraethoxysilane-oxygen (TEOS-O
₂ ) Oxide film 16 formed by plasma CVD method
Is a similar cross-sectional view obtained under the same conditions as in Example 2 except that the oxide film is deposited, but it can be seen that this oxide film has poor adhesion to the photoresist.

[0027]

According to the present invention, an oxide film having excellent adhesion to a photoresist film can be formed as a lower layer, and this can be used as an adhesion layer or a taper etch layer for wet etching. It is possible to prevent intrusion of a developing solution and an etching solution in a photolithography process due to poor adhesion between a thin film such as an interlayer insulating film and a resist film, and as a result, the resist film does not peel off or undercut, so that etching is not performed. A good taper angle can be formed around the opening.

Further, wet etching exhibiting good isotropy without fear of side etching can be performed, and a wet etching method suitable for a design rule for miniaturization can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a wet-etched portion showing an embodiment according to the present invention.

FIG. 2 is a sectional view of a wet-etched portion showing another embodiment according to the present invention.

FIG. 3 is a cross-sectional view of a hole portion for explaining a contact hole forming step in a conventional semiconductor device.

FIG. 4 is a cross-sectional view showing an undercut state according to a conventional example.

FIG. 5 is a cross-sectional view of a portion that has been wet-etched by a pretreatment method different from that of the embodiment of the present invention.

FIG. 6 is a cross-sectional view of a portion that has been wet-etched by another pretreatment method different from the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2, 10 lower wiring 3 interlayer insulating film 4, 12 resist film 5 upper opening 6 lower opening 7 contact hole 8, 15 undercut 11 BPSG film 13 oxide film 14 opening

Continuation of the front page (72) Inventor Yutaka Masuda 1580 Yamamoto, Tateyama-shi, Chiba NMB Semiconductor Co., Ltd. (56) References JP-A-3-141632 (JP, A) JP-A-2-290012 ( JP, A) JP-A-3-274720 (JP, A) JP-A-4-15910 (JP, A) JP-A-2-246320 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , (DB name) H01L 21/027

Claims (1)

(57) [Claims] 1. A method of forming a photoresist film on a thin film formed on a semiconductor substrate, forming the photoresist film into a desired pattern, and performing wet etching using the photoresist film as a mask. A pre-wet etching method for a semiconductor device, further comprising the step of forming an oxide film on the thin film by a plasma vapor deposition method using an oxidation reaction of monosilane (SiH ₄ ).