KR100499410B1 - Method for forming shallow trench isolating film of semiconductor device - Google Patents
Method for forming shallow trench isolating film of semiconductor device Download PDFInfo
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- KR100499410B1 KR100499410B1 KR10-2003-0008271A KR20030008271A KR100499410B1 KR 100499410 B1 KR100499410 B1 KR 100499410B1 KR 20030008271 A KR20030008271 A KR 20030008271A KR 100499410 B1 KR100499410 B1 KR 100499410B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
Abstract
본 발명은 반도체소자의 소자분리막 형성 방법을 개시한다. 개시된 발명은, 실리콘기판상에 패드산화막과 패드질화막 및 OBARC박막을 적층한후 그 위에 소자 분리막 영역을 한정하는 감광막패턴을 형성하는 단계; 상기 감광막패턴을 마스크로 상기 패드질화막상면이 드러날 때까지 OBARC박막을 선택적으로 식각하는 단계; 상기 OBARC박막을 선택적으로 식각한후 폴리머 비발생공정을 진행하여 패드질화막을 과도식각하는 단계; 및 추가 과도식각공정을 진행하여 패드산화막과 실리콘기판을 선택적으로 식각하여 상기 실리콘기판내에 트렌치를 형성하는 단계를 포함하여 구성되어, 기존의 폴리머 리치공정을 병행하여 실리콘 상부의 라운딩을 형성시키 므로써 실리콘의 언에치(unetch)를 제거할 수 있는 것이다.The present invention discloses a method of forming a device isolation film of a semiconductor device. The disclosed invention comprises the steps of: depositing a pad oxide film, a pad nitride film, and an OBARC thin film on a silicon substrate, and then forming a photoresist pattern defining a device isolation region thereon; Selectively etching the OBARC thin film using the photoresist pattern as a mask until the upper surface of the pad nitride film is exposed; Selectively etching the OBARC thin film and then performing a non-polymerization process to overetch the pad nitride film; And forming a trench in the silicon substrate by selectively etching the pad oxide film and the silicon substrate by performing an additional transient etching process, by forming a rounding of the silicon upper part in parallel with the existing polymer rich process. You can get rid of the unetch.
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로서, 보다 상세하게는 기존의 폴리머 리치공정을 병행하여 실리콘 상부의 라운딩을 형성시키므로써 실리콘의 언에치(unetch)를 제거할 수 있는 반도체소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a semiconductor device capable of removing an unetch of silicon by forming a rounding of silicon on top of a conventional polymer rich process. The present invention relates to a device isolation film forming method.
최근에는 0.18 μm 이하 기술에서 베어(bare) 실리콘웨이퍼위에 소자분리막을형성하기 위하여 실리콘기판을 식각하는 일명 트렌치 식각을 실시하고 있다.Recently, in the technology of 0.18 μm or less, a trench etching is performed to etch a silicon substrate to form an isolation layer on a bare silicon wafer.
이와 같은 종래의 실리콘기판의 트렌치 식각공정에 대해 도 1를 참조하여 설명하면 다음과 같다.The trench etching process of the conventional silicon substrate will be described with reference to FIG. 1 as follows.
도 1a 및 도 1c는 종래기술에 따른 실리콘기판의 트렌치 식각공정을 설명하기 위한 공정단면도이다.1A and 1C are cross-sectional views illustrating a trench etching process of a silicon substrate according to the prior art.
종래기술에 따른 실리콘기판내에 트렌치를 형성하는 공정에 대해 설명하면, 도 1a에 도시된 바와같이, 실리콘기판(11)상에 소정두께의 패드산화막(13)과 패드질화막(15) 및 OBARC(Organic Bottom Anti Reflection Coating)박막(17)을 차례로 증착한후 그 위에 감광막(19)을 도포한다.A process of forming a trench in a silicon substrate according to the prior art will be described. As shown in FIG. 1A, a pad oxide film 13, a pad nitride film 15, and an OBARC (Organic) having a predetermined thickness on a silicon substrate 11 are illustrated. Bottom Anti Reflection Coating) thin film 17 is sequentially deposited and then a photosensitive film 19 is applied thereon.
그다음, 도 1b에 도시된 바와같이, 상기 감광막(19)을 포토리쏘그라피공정기술에 의한 노광 및 현상공정을 통해 선택적으로 제거하여 소자분리막 영역을 한정하는 감광막패턴(19a)을 형성한다.Next, as shown in FIG. 1B, the photoresist film 19 is selectively removed through an exposure and development process by a photolithography process technology to form a photoresist pattern 19a defining an element isolation layer region.
이어서, 도 1c에 도시된 바와같이, 상기 감광막패턴(19a)을 마스크로 CHF3/CF4/Cl2/O2/Ar 등의 가스를 이용하여 상기 OB ARC박막(17)과 패드질화막(15) 및 패드산화막(13)을 순차적으로 제거하고 이어 실리콘기판(11)을 일정깊이만큼 과도식각하여 상기 실리콘기판(11)내에 트렌치(21)를 형성한다. 이때, 상기 OB ARC박막(17)과 패드질화막(15)의 일부는 CHF3/CF4/O2로 식각하고, 남아 있는 패드질화막(15)과 패드산화막(13) 및 실리콘기판(11)에 대한 소정의 과도식각은 CHF3/CF4/Ar 가스로 식각한다.Subsequently, as shown in FIG. 1C, the OB ARC thin film 17 and the pad nitride film 15 are formed by using a gas such as CHF 3 / CF 4 / Cl 2 / O 2 / Ar as the photosensitive film pattern 19a as a mask. ) And the pad oxide film 13 are sequentially removed, and the silicon substrate 11 is excessively etched to a predetermined depth to form the trench 21 in the silicon substrate 11. At this time, a part of the OB ARC thin film 17 and the pad nitride film 15 is etched with CHF 3 / CF 4 / O 2 , and the remaining pad nitride film 15, the pad oxide film 13, and the silicon substrate 11 are etched. Predetermined transient etching is performed with CHF 3 / CF 4 / Ar gas.
상기에서와 같이, 종래기술에 의하면 도 1c의 "A"와 같은 콘 결함(corn defect)은 OB ARC박막과 패드질화막 및 실리콘기판식각시에 발생하는 폴리머에 의해 발생하게 된다. 즉, 도 1c의 "B"와 같은 인위적인 실리콘상부 라운딩을 주기 위하여 CHF3 가스 등을 사용하여 과도한 폴리머를 발생시키고 이러한 폴리머가 OBARC박막과 패드질화막 식각시 콘결함을 유발시키는 원인(seed)을 제공하고, 이후 실리콘기판의 과도식각시에 상기 시드(seed)가 배리어로 작용하여 도 1c의 "A"와 같은 콘결함을 유발시킨다.As described above, according to the prior art, a corn defect such as "A" of FIG. 1C is caused by a polymer generated during etching of the OB ARC thin film, the pad nitride film, and the silicon substrate. In other words, CHF 3 gas or the like is used to give an artificial upper silicon rounding, such as "B" of FIG. Then, when the silicon substrate is excessively etched, the seed acts as a barrier, resulting in concave defects such as "A" of FIG. 1C.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 기존과 달리 폴리머 비발생 공정을 적용하면서 실리콘 상부의 라운딩을 형성 시키므로써 실리콘의 언에치(unetch)를 제거할 수 있는 반도체소자의 소자분리막 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in order to solve the above problems of the prior art, and unlike the conventional semiconductor that can remove the unetch (silicon) by forming a rounding of the upper silicon while applying a polymer-free process It is an object of the present invention to provide a method for forming a device isolation film of a device.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성 방법은 실리콘기판 상에 패드 산화막과 패드 질화막 및 OBARC박막을 차례로 적층한후, 상기 OBARC박막 위에 소자분리막 영역을 한정하는 감광막패턴을 형성하는 제 1단계; 감광막패턴을 마스크로 상기 패드 질화막 상면이 드러날 때까지 상기 OBARC박막을 선택적으로 식각하는 제 2단계; 패드 질화막이 드러나는 순간 상기 결과물에 CF4 및 O2가스를 공급시켜 상기 잔류된 OBARC박막에 대한 과도식각하면서 상기 패드질화막을 식각하여 상기 OBARC박막과 패드질화막 간의 시드를 제거하는 제 3단계: 3단계가 완료된 다음, CH4 및 Ar가스를 추가로 공급시켜 상기 잔류된 패드 질화막을 과도식각하는 제 4단계;및 4단계가 완료된 다음, 상기 패드 산화막 및 실리콘기판을 선택적으로 식각하여 상기 실리콘기판 내에 트렌치를 형성과 동시에 상기 트렌치 상부에 라운딩부를 형성하는 제 5단계를 포함하는 것을 특징으로 한다. 상기 제 2단계의 식각 공정조건은 CHF3/CF4/O2 가스를 이용하고, 약 80 mTorr 정도의 압력과 약 300 W 정도의 파워를 이용한다.상기 제 3단계의 식각 공정조건은 80 mTorr 압력과 300 W 파워를 이용한다. 상기 제 4단계의 식각 공정조건은 40 mTorr 압력과 700W 파워를 이용한다. 상기 5단계의 식각 공정조건은 CF4, CHF3 및 Ar 가스를 이용하고, 40 mTorr의 압력과 700 W의 파워를 이용한다.In the method of forming a device isolation film of a semiconductor device according to the present invention for achieving the above object, a pad oxide film, a pad nitride film, and an OBARC thin film are sequentially stacked on a silicon substrate, and then a photosensitive film pattern defining a device isolation film region is formed on the OBARC thin film. The first step to do; A second step of selectively etching the OBARC thin film using a photoresist pattern as a mask until the top surface of the pad nitride film is exposed; The third step of removing the seed between the OBARC thin film and the pad nitride film by etching the pad nitride film while over-etching the remaining OBARC thin film by supplying CF4 and O2 gas to the resultant at the time the pad nitride film is revealed. A fourth step of over-etching the remaining pad nitride film by additionally supplying CH4 and Ar gas; and after the fourth step is completed, selectively etching the pad oxide film and the silicon substrate to form a trench in the silicon substrate; And at the same time, forming a rounding part on the trench. The etching process condition of the second step uses a CHF 3 / CF 4 / O 2 gas, a pressure of about 80 mTorr and a power of about 300 W. The etching process of the third step is 80 mTorr pressure And 300 W power. The etching process condition of the fourth step uses a 40 mTorr pressure and 700W power. The etching process conditions of the fifth step is CF 4 , CHF 3 And Ar gas, using a pressure of 40 mTorr and a power of 700 W.
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이하, 본 발명에 따른 반도체소자의 소자분리막 형성 방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 소자분리막 형성방법은, 도 2a에 도시된 바와같이, 먼저 실리콘기판(31)상에 소정두께의 패드산화막(33)과 패드질화막(35) 및 OBARC박막(37)을 차례로 증착한후 그 위에 감광막(39)을 도포한다.In the method of forming a device isolation film of a semiconductor device according to the present invention, as shown in FIG. 2A, a pad oxide film 33, a pad nitride film 35, and an OBARC thin film 37 having a predetermined thickness are first formed on a silicon substrate 31. After the deposition in turn, a photosensitive film 39 is applied thereon.
그다음, 도 2b에 도시된 바와같이, 상기 감광막(39)을 포토리쏘그라피공정기술에 의한 노광 및 현상공정을 통해 선택적으로 제거하여 소자분리막 영역을 한정하는 감광막패턴(39a)을 형성한다.Next, as shown in FIG. 2B, the photoresist film 39 is selectively removed through an exposure and development process using a photolithography process technology to form a photoresist pattern 39a defining an element isolation layer region.
이어서, 상기 감광막패턴(39a)을 마스크로 CHF3/CF4/O2 가스를 이용하여 상기 패드질화막(35)상면이 드러날 때까지 상기 OB ARC박막(37)을 식각한다. 이때, 상기 식각시 공정조건으로는 약 80mTorr의 압력과 300W 정도의 파워를 사용한다.Subsequently, the OB ARC thin film 37 is etched by using the CHF 3 / CF 4 / O 2 gas as the mask until the top surface of the pad nitride film 35 is exposed. At this time, the etching process conditions using a pressure of about 80mTorr and a power of about 300W.
그다음, 도 2c에 도시된 바와같이, 상기 패드질화막(35)상면이 드러나는 순간 제1폴리머 비발생공정(non-polymer process)을 진행한다. 이때, 상기 제1폴리머 비발생 공정은 상기 OBARC박막(39a)과 패드질화막(37)간의 시드(seed)를 제거하기 위해 진행하며, 제1폴리머 비발생 공정을 진행하기 위해 먼저 주 폴리머 소스인 CHF3 가스를 제외한 CF4/O2 가스를 이용한다. 즉, 제1폴리머 비발생 공정으로 OBARC박막에 대한 과도식각과 패드질화막을 제거한다. 이때, 상기 제1 폴리머 비발생 공정조건으로는 약 80mTorr의 압력과 300W 정도의 파워를 사용한다.Then, as shown in FIG. 2C, the first polymer non-polymer process is performed at the moment when the top surface of the pad nitride layer 35 is exposed. In this case, the first polymer non-generating process proceeds to remove seeds between the OBARC thin film 39a and the pad nitride layer 37, and CHF, which is a main polymer source, is first used to proceed with the first polymer non-generating process. Use CF 4 / O 2 gas except 3 gases. That is, the over-etching of the OBARC thin film and the pad nitride film are removed by the first polymer non-generating process. In this case, as the first polymer non-generating process condition, a pressure of about 80 mTorr and a power of about 300 W are used.
이어서, CF4/Ar 가스를 이용한 제2폴리머 비발생공정을 진행하여 상기 패드질화막(35)을 과도식각한다. 이때, 상기 제2 폴리머 비발생 공정조건으로는 약 40mTorr 정도의 압력과 700W 정도의 파워를 사용한다.Subsequently, CF 4 / Ar The pad nitride layer 35 is excessively etched by performing a second polymer non-generating process using a gas. In this case, as the second polymer non-generating process condition, a pressure of about 40 mTorr and a power of about 700 W are used.
그다음, 도2e에 도시된 바와같이, 추가로 과도식각공정을 진행하여 패드산화막(33)과 실리콘기판(11)을 일정깊이만큼 과도식각하여 상기 실리콘기판(31)내에 트렌치(41)를 형성함과 동시에 트렌치 상부 라운딩부(C)를 형성하게 된다. 이때, 상기 추가 과도식각공정시에 CHF3/CF4/Ar 가스를 이용하며, 약 40mTorr 정도의 압력과 700W 정도의 파워를 사용한다.Next, as shown in FIG. 2E, the over etching process is further performed to overetch the pad oxide layer 33 and the silicon substrate 11 to a predetermined depth to form the trench 41 in the silicon substrate 31. At the same time, the trench upper rounding part C is formed. In this case, CHF 3 / CF 4 / Ar gas is used in the additional transient etching process, and a pressure of about 40 mTorr and a power of about 700 W are used.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 소자분리막 형성방법에 의하면, 기존과 달리 폴리머 비발생 리치공정을 먼저 진행하여 콘결함(corn defect)을 발생시키는 소스(seed)를 제거하고 이후 기존의 폴리머 리치 공정을 병행하여 실리콘 상부의 라운딩을 형성시키므로써 실리콘 언에치(unetch)를 유발하는 소스를 제거할 수 있다.As described above, according to the method of forming a device isolation film of a semiconductor device according to the present invention, unlike the conventional method, a polymer-free rich process is first performed to remove a source that generates a corn defect, and then a conventional method. It is possible to remove the source causing the silicon unetch by forming a round of silicon on top of the polymer rich process.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1a 및 도 1c는 종래기술에 따른 실리콘기판의 트렌치 식각공정을 설명하기 위한 공정단면도,1A and 1C are cross-sectional views illustrating a trench etching process of a silicon substrate according to the prior art;
도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도.2A to 2E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 실리콘기판 33 : 패드산화막31 silicon substrate 33 pad oxide film
35 : 패드질화막 37 : OBARC박막35 pad nitride film 37 OBARC thin film
39 : 감광막 41 : 트렌치 39: photosensitive film 41: trench
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