JPS6143847B2 - - Google Patents
Info
- Publication number
- JPS6143847B2 JPS6143847B2 JP11070377A JP11070377A JPS6143847B2 JP S6143847 B2 JPS6143847 B2 JP S6143847B2 JP 11070377 A JP11070377 A JP 11070377A JP 11070377 A JP11070377 A JP 11070377A JP S6143847 B2 JPS6143847 B2 JP S6143847B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- substrate
- polycrystalline silicon
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000005684 electric field Effects 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 37
- 239000007789 gas Substances 0.000 description 25
- 238000000992 sputter etching Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000000576 coating method Methods 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 7
- 238000010884 ion-beam technique Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 3
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 3
- 150000003377 silicon compounds Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、任意の
種類の微細パターンを写真蝕刻法によらず簡便か
つ制御性良く形成する新規な方法を提供すること
を目的とするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices, and an object of the present invention is to provide a new method for forming any type of fine pattern simply and with good controllability without using photolithography. be.
半導体装置は最近ますます高密度化される傾向
にあり、そのために微細パターン形成法の開発に
対する要望が高まつている。従来一般に紫外線に
よる写真蝕刻法が用いられてきたが、実用的な最
小パターン巾は２ミクロン程度とされている。そ
れ以下の微細パターン形成に適した方法として電
子ビーム露光法やＸ線露光法が開発されつつある
が未だ十分実用に供されるに到つていない。その
上、ただ単に微細なパターンを形成するだけでな
く、既に形成されている形状に位置合せする必要
のある場合に、その位置合せ誤差を皆無にするこ
とは写真蝕刻法では極めて困難である。さて、微
細パターンを得るべく段部にあるパターンを形成
するに際し、従来の方法を用いた例を第１図とと
もに説明する。第１図は従来方法すなわち位置合
せを要する場合の微細パターンの形成について説
明する。 2. Description of the Related Art Recently, semiconductor devices are becoming more and more densely packed, and as a result, there is an increasing demand for the development of fine pattern forming methods. Conventionally, photolithography using ultraviolet rays has been generally used, but the practical minimum pattern width is about 2 microns. Electron beam exposure methods and X-ray exposure methods are being developed as methods suitable for forming finer patterns than this, but they have not yet been put to practical use. Furthermore, when it is necessary not only to simply form a fine pattern but also to align it with an already formed shape, it is extremely difficult to eliminate alignment errors using photolithography. Now, an example in which a conventional method is used to form a pattern on a stepped portion to obtain a fine pattern will be described with reference to FIG. FIG. 1 explains the conventional method, that is, the formation of fine patterns when alignment is required.
第１図ａのごとく、半導体基板１表面に段部２
を形成し次に表面に熱酸化法あるいはCVD法に
よつて酸化膜３を形成する。ついで、第１図ｂ
は、前記基板１表面に酸化膜３を形成後、気相成
長法例えば、650℃でSiH4ガスの熱分解による多
結晶シリコン膜４を成長させたものである。 As shown in FIG. 1a, a stepped portion 2 is formed on the surface of the semiconductor substrate 1.
Then, an oxide film 3 is formed on the surface by thermal oxidation or CVD. Next, Figure 1b
After forming an oxide film 3 on the surface of the substrate 1, a polycrystalline silicon film 4 is grown by vapor phase growth, for example, by thermal decomposition of SiH 4 gas at 650°C.
同図ｃでは、多結晶シリコン膜４上から光感光
性樹脂例えば、ネガレジスト５をスピナー回転塗
布等の方法で全面に塗布する。次に同図ｄで示す
ごとく、ネガレジスト５を残存させる部分８のみ
紫外線６が透過するガラス乾板７を重ね合せネガ
レジスト５を光重合せしめる。 In FIG. 3c, a photosensitive resin, for example, a negative resist 5, is applied over the entire surface of the polycrystalline silicon film 4 by spinner rotation coating or the like. Next, as shown in FIG. 4D, a glass dry plate 7 through which ultraviolet rays 6 pass only in the portion 8 where the negative resist 5 remains is superimposed, and the negative resist 5 is photopolymerized.
同図ｅはネガレジスト５を光重合した後、現像
し光重合以外の部分は溶解させ、段部２の部分に
レジストパターン８を形成した状態である。 Figure e shows a state in which the negative resist 5 is photopolymerized, then developed, and the portions other than the photopolymerized portions are dissolved to form a resist pattern 8 in the stepped portion 2.
同図ｆは、レジストパターン８をマスクに多結
晶シリコン膜をエツチング除去したものである。
レジストパターン８下の多結晶シリコン膜４は、
エツチングされずに残存する。 Figure f shows the polycrystalline silicon film removed by etching using the resist pattern 8 as a mask.
The polycrystalline silicon film 4 under the resist pattern 8 is
It remains unetched.
同図ｇは、多結晶シリコン膜４のエツチング
後、レジストパターンを熱濃硫酸あるいは、レジ
スト剥離剤等で除去した状態を示す。 FIG. 1g shows a state in which the resist pattern has been removed using hot concentrated sulfuric acid, a resist stripping agent, etc. after etching the polycrystalline silicon film 4.
以上の例は本発明のごとき段部へのパターン形
成に際し、従来の方法を適用した理想的な場合を
示したものであつて現在の技術水準では、たとえ
電子ビーム露光を用いてもレジストパターン８と
段部２とを完全に一致させることは困難であり、
実際上はこうして形成された多結晶シリコン膜４
と段部２との間に間隙あるいは重なり部分を生じ
る。 The above example shows an ideal case in which a conventional method is applied when forming a pattern on a stepped portion as in the present invention. It is difficult to completely match the step part 2 with the step part 2,
Actually, the polycrystalline silicon film 4 formed in this way
A gap or an overlapping portion is created between the step portion 2 and the step portion 2.
またそもそも写真蝕刻法にするため、ガラス乾
板が必要であり、レジスト塗布・露光・現像・エ
ツチング・レジスト除去等少くとも五工程を要す
る。さらに、最終の多結晶シリコン膜４のパター
ン巾がレジストパターン８の巾に依存しているた
め、レジストの膜厚・露光及現像条件等多くの要
因の制御が精密なパターン巾形成のために必要で
ある。 Furthermore, in order to use the photolithography method, a glass drying plate is required, and at least five steps are required, including resist coating, exposure, development, etching, and resist removal. Furthermore, since the pattern width of the final polycrystalline silicon film 4 depends on the width of the resist pattern 8, it is necessary to control many factors such as resist film thickness, exposure and development conditions, etc. to form a precise pattern width. It is.
そこで写真蝕刻法によらずに微細パターンを形
成する方法が最近種々提案されている。例えば、
特開昭50−110778号公報には、第１図ａの如く段
部を有する半導体基板表面に、シラノール（Si
（OH）4）の如き液状のシリコン化合物を塗布し
て、段部２の近傍により多くその液体が滞留する
ことを利用する方法がある。この方法ではその液
体を塗布後、加熱処理を行なつて二酸化シリコン
膜を形成し、しかるのち弗化水素系のエツチング
液によりその二酸化シリコン層をエツチする。そ
の際、段部２近傍に於てはシリコン化合物の液が
滞留した事により二酸化シリコン層が厚くなつて
いるため、その二酸化シリコン層のみが残存する
如くエツチングを行うことが出来る。かくして段
部２の近傍のみを覆う如く、自己整合的に二酸化
シリコン層が形成される。この方法は写真蝕刻法
によらずに比較的簡単に微細パターンが形成され
るという利点を有しているが、液体の塗布が必須
であるためどの様な被膜でも形成出来る訳ではな
く適用範囲がきわめて狭い。またこの方法で段部
に形成される二酸化シリコン層のパターン巾は、
シリコン化合物の段部に於ける滞留状態に主とし
て依存しているため、液の粘度・塗布条件・段部
の段差およびその表面状態等多くの微妙な要因に
左右される。従つてパターン巾を精度よく形成す
るのに適していない。 Therefore, various methods for forming fine patterns without using photolithography have recently been proposed. for example,
JP-A-50-110778 discloses that silanol (Si
There is a method of applying a liquid silicon compound such as (OH) 4 ) and utilizing the fact that more of the liquid stays near the stepped portion 2. In this method, after applying the liquid, a heat treatment is performed to form a silicon dioxide film, and then the silicon dioxide layer is etched using a hydrogen fluoride-based etching solution. At this time, since the silicon dioxide layer has become thick near the step portion 2 due to the retention of the silicon compound liquid, etching can be performed so that only the silicon dioxide layer remains. In this way, a silicon dioxide layer is formed in a self-aligned manner so as to cover only the vicinity of the step portion 2. This method has the advantage that fine patterns can be formed relatively easily without using photolithography, but since it requires liquid application, it is not possible to form any kind of film, and the range of application is limited. Extremely narrow. In addition, the pattern width of the silicon dioxide layer formed at the step by this method is
Since it mainly depends on the retention state of the silicon compound in the stepped portion, it is influenced by many subtle factors such as the viscosity of the liquid, the coating conditions, the difference in level between the steps, and its surface condition. Therefore, it is not suitable for forming a pattern width with high precision.
また、基板表面に斜めにイオンビームを入射せ
しめる方法が特開昭50−66183号に提案されてい
る。これは基板上に設けられた段部に被膜を成長
せしめ、斜め上方からイオンビームを入射せしめ
てその被膜をイオンエツチすると、イオンビーム
の直進性により段部側面にイオンビームが到達し
ない影の部分が生じるため被膜の微細パターンが
形成される。その被膜の微細パターンの巾は段部
の段差とイオンビームの入射角度で規定される。
この方法では、基板表面の上方から見た場合ビー
ムの入射方向と平行に走る段部側面からは被膜が
すべて除去されてしまう。というのはこの場合段
部に影が出来ないからである。すなわちこの方法
では被膜の微細パターンを任意の方向に形成する
事が出来ない。したがつて半導体装置のパターン
設計に大きな制限を加えることになり適用対象が
限定されたものとなる。 Further, a method of making an ion beam incident on the substrate surface obliquely has been proposed in Japanese Patent Laid-Open No. 66183/1983. This is because a film is grown on a step provided on a substrate, and when the ion beam is incident diagonally from above to ion-etch the film, due to the straightness of the ion beam, there are shadowed areas where the ion beam does not reach the side of the step. As a result, a fine pattern of the film is formed. The width of the fine pattern of the coating is determined by the step difference and the incident angle of the ion beam.
In this method, the coating is completely removed from the side surfaces of the stepped portion that run parallel to the direction of incidence of the beam when viewed from above the substrate surface. This is because in this case no shadow is formed on the step. That is, with this method, it is not possible to form a fine pattern of the film in any direction. Therefore, a large restriction is placed on the pattern design of the semiconductor device, and the objects to which it can be applied are limited.
従来のこの様な種々の問題を解決するための本
発明の構成は、半導体基板表面に段部を設け、該
基板表面段部の上面・底面および側面にCVD法
あるいは蒸着法などによる被膜を堆積形成させた
後、該基板をガスエツチング装置内に入れ、エツ
チングガスを基板にほぼ垂直に入射せしめ、該基
板表面に垂直方向へのエツチングを選択的に進行
せしめ、段部の上面および底面の被膜を全て除去
して、段部の側面およびその近傍のみに上記被膜
を残存せしめることから成る。本発明はこのよう
な方法を用いることにより、段部に微細パターン
を写真蝕刻法によらず制御性良く形成可能とした
ものである。 The structure of the present invention to solve various conventional problems is to provide a step on the surface of a semiconductor substrate, and deposit a film on the top, bottom, and side surfaces of the step on the substrate surface by CVD or vapor deposition. After forming the etching, the substrate is placed in a gas etching device, and the etching gas is applied almost perpendicularly to the substrate to selectively proceed with etching in the direction perpendicular to the surface of the substrate, thereby removing the coating on the top and bottom surfaces of the stepped portions. The step consists of removing all of the coating, leaving the coating only on the side surfaces of the stepped portions and in the vicinity thereof. By using such a method, the present invention makes it possible to form a fine pattern on the stepped portion with good controllability without using photolithography.
以下本発明を実施例とともに説明する。 The present invention will be explained below along with examples.
第２図は本発明を用いて多結晶シリコンよりな
るたとえばMOSトランジスタのゲートパターン
を形成する工程を示す。 FIG. 2 shows a process of forming a gate pattern of, for example, a MOS transistor made of polycrystalline silicon using the present invention.
第２図ａは半導体基板２１の未加工の状態が示
してある。図ｂは半導体基板２１の表面に上面２
５、側面２６、底面２７から成る段部２２を形成
したものである。この段部２２の側面２６は、基
板２１の表面に対してほぼ垂直に形成するのが望
しく、例えばイオンビームを用いるイオンエツチ
あるいはフレオン系ガスをプラズマ状にしさらに
試料に電界を印加する反応性スパツタエツチング
等により行なう。なお、反応性スパツタエツチン
グまたは反応性イオンエツチング等でエツチング
を行なう場合、エツチング断面をほぼ垂直にする
にはスパツタ性を強くすれば得られる。例えば、
フレオン１２（CCl2F2）ガスを使用し、真空度
0.01Torr、出力400W、フレオン１２のガス流量
を10c.c.／Ｍ程度としエツチングを行なうとエツチ
ング断面は、ほぼ垂直に形成される。またフレオ
ンの代わりに四塩化炭素（CCl4）ガスを使用して
も同等の形状を得ることができる。 FIG. 2a shows the semiconductor substrate 21 in its unprocessed state. Figure b shows the upper surface 2 on the surface of the semiconductor substrate 21.
5. A stepped portion 22 consisting of a side surface 26 and a bottom surface 27 is formed. The side surface 26 of this stepped portion 22 is desirably formed almost perpendicularly to the surface of the substrate 21. For example, ion etching using an ion beam or reactive spacing using a Freon-based gas in the form of plasma and applying an electric field to the sample is preferable. This is done by ivy etching etc. Note that when etching is performed by reactive sputter etching or reactive ion etching, the etching cross section can be made substantially vertical by increasing sputtering properties. for example,
Freon 12 (CCl 2 F 2 ) gas is used, and the degree of vacuum is
When etching is performed at 0.01 Torr, an output of 400 W, and a Freon 12 gas flow rate of about 10 c.c./M, the etched cross section is formed almost vertically. Furthermore, the same shape can be obtained by using carbon tetrachloride (CCl 4 ) gas instead of Freon.
次に同図ｂに示すごとくほぼ垂直な側面２６を
有する段部２２を設けた半導体基板上に熱酸化法
あるいはCVD法等により酸化膜２３を形成す
る。そして、同図ｃはのごとく酸化膜２３上に気
相成長法等により多結晶シリコン膜２４を成させ
る。この多結晶シリコン膜の成長は、例えば650
℃の温度でN2ガスを30／Ｍ、シラン（SiH4）ガ
スを１／Ｍ流した状態で行なう。段部２２の上
面２５および底面２７上に於けるとほぼ同じく側
面２６上に於ても多結晶シリコンが成長する。そ
の結果、多結晶シリコン膜２４の表面は、段部２
２の上面２５・底面２７・側面２６にそれぞれ沿
つた面２５′，２６′，２７′から成る。この時、
半導体基板２１の表面、すなわち上面２５および
底面２７に垂直方向に、多結晶シリコン膜２４の
膜厚を見ると、段部２２の側面２６近傍に於ては
膜厚が段差の分だけ厚くなつていることになる。 Next, as shown in FIG. 1B, an oxide film 23 is formed by thermal oxidation, CVD, or the like on the semiconductor substrate provided with a stepped portion 22 having substantially vertical side surfaces 26. Then, as shown in FIG. 3C, a polycrystalline silicon film 24 is formed on the oxide film 23 by vapor phase growth or the like. The growth of this polycrystalline silicon film is, for example, 650
The test is carried out at a temperature of 0.degree. C. under a flow of 30/M N 2 gas and 1/M silane (SiH 4 ) gas. Polycrystalline silicon grows on the side surface 26 as well as on the top surface 25 and bottom surface 27 of the stepped portion 22 . As a result, the surface of the polycrystalline silicon film 24 is
It consists of surfaces 25', 26', and 27' along the top surface 25, bottom surface 27, and side surface 26 of 2, respectively. At this time,
Looking at the film thickness of the polycrystalline silicon film 24 in the direction perpendicular to the surface of the semiconductor substrate 21, that is, the top surface 25 and the bottom surface 27, the film thickness near the side surface 26 of the stepped portion 22 becomes thicker by the difference in step. There will be.
しかるのち、同図ｄは、同図ｃで表面に均一に
形成した多結晶シリコン膜上からエツチングガス
２８をほぼ垂直に入射せしめた状態を示す。この
ようにすると多結晶シリコン膜の側面２６′上へ
到達するエツチングガスの量が少ないので、その
面のエツチ速度が小さい。これは面２６′の同図
上での左方への後退が少ない事を意味する。即ち
膜２４は基板表面と平行面をなす如く層状にエツ
チされていく。このドライエツチングとして、例
えば反応性スパツタエツチングを用いる。その場
合スパツタ性向上のため、真空度は0.03Torr以上
の高真空側で、出力は400W程度とし、エツチン
グガスにフレオン１２（CCl2F2）を使用し流量は
10c.c.／Ｍ程度で行なう。 Thereafter, Figure d shows the state in which the etching gas 28 is made to enter almost perpendicularly from above the polycrystalline silicon film that has been uniformly formed on the surface in Figure 3c. In this way, the amount of etching gas that reaches the side surface 26' of the polycrystalline silicon film is small, so the etching rate on that surface is low. This means that the surface 26' recedes less to the left in the same figure. That is, the film 24 is etched in layers so as to form a plane parallel to the substrate surface. As this dry etching, for example, reactive sputter etching is used. In that case, in order to improve sputtering, the degree of vacuum should be on the high vacuum side of 0.03 Torr or higher, the output should be about 400 W, Freon 12 (CCl 2 F 2 ) was used as the etching gas, and the flow rate should be
Do this at around 10c.c./M.
以上の工程により、同図ｅに示すごとく半導体
基板の段部上面２５、および底面２７の多結晶シ
リコン膜をエツチング除去すると、段部の側面２
６には、段部の高さとほぼ同一高さＬで、また多
結晶シリコンの成長膜厚とほぼ同一な巾Ｗを有す
る多結晶シリコン２４′が残る。多結晶シリコン
膜２４下の酸化膜２３は、反応性スパツタエツチ
ングの際のストツパー及び多結晶シリコンのエツ
チング終了の目安に使用しているが、他の被膜あ
るいは被膜を設置しなくても良い。 Through the above process, as shown in FIG.
6, polycrystalline silicon 24' remains, which has a height L that is approximately the same as the height of the step portion and a width W that is approximately the same as the thickness of the grown polycrystalline silicon. The oxide film 23 under the polycrystalline silicon film 24 is used as a stopper during reactive sputter etching and as a guide for finishing etching of polycrystalline silicon, but other films or films may not be provided.
この説明では、シリコン基板に酸化膜と多結晶
シリコンの組合せで行なつたが、これに限らず、
酸化膜あるいは窒化膜等、任意の膜種を任意の膜
厚で段部に堆積形成することも可能である。 In this explanation, we used a combination of oxide film and polycrystalline silicon on a silicon substrate, but the invention is not limited to this.
It is also possible to deposit any type of film, such as an oxide film or a nitride film, to any thickness on the stepped portion.
第３図は、本発明の要部である第２図の工程中
のｄの拡大図である。 FIG. 3 is an enlarged view of d during the process of FIG. 2, which is the main part of the present invention.
図中のtoは多結晶シリコン膜２４成長後の膜厚
の位置を示す線である。エツチングガス２８はフ
レオン系ガスをプラズマ状として発生した主とし
てフツ素ラジカルであり、多結晶シリコンをエツ
チングするものであるが、反応性スパツタエツチ
ングではその条件により、基板表面に対してほぼ
垂直にフツ素ラジカルを入射せしめ得るため平面
部２５′および２７′には多くフツ素ラジカルが入
射し、側面部２６′へはフツ素ラジカルが殆んど
入射しないことになる。このため面２５′および
２７′ではエツチングが進み側面２６′では殆んど
エツチングが進まないことになる。 In the figure, to is a line indicating the position of the film thickness after the polycrystalline silicon film 24 is grown. The etching gas 28 is mainly fluorine radicals generated from Freon-based gas in the form of plasma, and is used to etch polycrystalline silicon. However, in reactive sputter etching, depending on the conditions, the etching gas 28 generates fluorine radicals that are generated almost perpendicularly to the substrate surface. In order to allow elementary radicals to be incident, many fluorine radicals are incident on the flat surfaces 25' and 27', and almost no fluorine radicals are incident on the side surface 26'. For this reason, etching progresses on the surfaces 25' and 27', while etching hardly progresses on the side surface 26'.
図中のt1は反応性スパツタエツチングを開始し
て一定時間経過した時の多結晶シリコンの形状図
であり、またt2はt1よりさら一定時間経過した時
の多結晶シリコンの形状図である。t3は段部２２
の上面２５及び底面２７上の多結晶シリコンを全
てエツチング除去し終えた時の形状図である。t3
時点で半導体基板の段部側面２６近傍のみに多結
晶シリコン２４′が形成される。この大きさは高
さが基板にあらかじめ形成した段差と同一で巾は
多結晶シリコンの成長膜厚とほぼ同じとなる。 In the figure, t 1 is a diagram of the shape of polycrystalline silicon after a certain period of time has elapsed since the start of reactive sputter etching, and t 2 is a diagram of the shape of polycrystalline silicon after a certain period of time has elapsed since starting reactive sputter etching. It is. t 3 is the stepped part 22
FIG. 3 is a diagram showing the shape when all the polycrystalline silicon on the top surface 25 and bottom surface 27 of the semiconductor device has been completely etched away. t 3
At this point, polycrystalline silicon 24' is formed only in the vicinity of the step side surface 26 of the semiconductor substrate. The height of this step is the same as that of a step previously formed on the substrate, and the width is approximately the same as the thickness of the grown polycrystalline silicon film.
気相成長法で成長せしめた多結晶シリコン膜を
一例とし詳細な説明を加えたが、本発明はその他
CVD法、連続した同一組成の金属膜や絶縁膜等
の他の被膜のパターンを形成する事も可能であ
る。 Although a detailed explanation has been given using a polycrystalline silicon film grown by a vapor phase growth method as an example, the present invention is applicable to other films as well.
It is also possible to form continuous patterns of other films such as metal films or insulating films with the same composition using the CVD method.
第４図は、本発明の実施例において使用するド
ライエツチング装置の概略図である。装置は、反
応部３１、真空部３２、高周波電源部３３、ガス
導入部３４より構成されている。反応部３１のチ
ヤンバー３５内のターゲツト３６上に試料３７を
設置する。次に真空部のロータリーポンプ３８お
よび拡散ポンプ３９によつてチヤンバー３５内を
真空にし、チヤンバー３５内のガス圧が規定の圧
力になつたらガス導入部３４より、反応ガスをチ
ヤンバー３５内に導入し、チヤンバー３５内を一
定の圧力に保持する。次に高周波電源部３３のス
イツチを入れ、チヤンバー３５内のターゲツト３
６と対向電極４０に高周波電界をかけ、反応ガス
をプラズマ状にし、さらにプラズマ状のガスを試
料３７表面に入射させるものである。 FIG. 4 is a schematic diagram of a dry etching apparatus used in an embodiment of the present invention. The apparatus includes a reaction section 31, a vacuum section 32, a high frequency power supply section 33, and a gas introduction section 34. A sample 37 is placed on a target 36 in a chamber 35 of a reaction section 31. Next, the inside of the chamber 35 is evacuated by the rotary pump 38 and the diffusion pump 39 in the vacuum section, and when the gas pressure inside the chamber 35 reaches a specified pressure, a reaction gas is introduced into the chamber 35 from the gas introduction section 34. , to maintain a constant pressure inside the chamber 35. Next, turn on the high frequency power supply section 33, and turn on the target 3 in the chamber 35.
A high-frequency electric field is applied to the sample 37 and the counter electrode 40 to turn the reaction gas into a plasma, and the plasma-like gas is made to enter the surface of the sample 37.
この装置で試料にほぼ垂直に入射する反応ガス
を多くするには、チヤンバー内を高真空にするか
高周波出力を大きくするかの２つの方法がある。
従つて真空度と出力を変化させることにより試料
には反応ガスを垂直に入射させることが出来る。 There are two ways to increase the amount of reactive gas that enters the sample almost perpendicularly with this device: create a high vacuum inside the chamber or increase the high-frequency output.
Therefore, by changing the degree of vacuum and output, the reactant gas can be made to enter the sample perpendicularly.
第５図は本発明の一応用例の製造工程である。
同図ａでは、既に説明した如く半導体基板２１に
段部２２を設け表面を酸化膜２３を形成し、さら
に多結晶シリコン膜を形成後、反応性スパツタエ
ツチングにより多結晶シリコン膜をエツチング除
去し、酸化膜２３の位置で停止したもので段部２
２には、多結晶シリコン２４′が形成されてい
る。 FIG. 5 shows the manufacturing process of one application example of the present invention.
In FIG. 1A, as already explained, a stepped portion 22 is provided on a semiconductor substrate 21, an oxide film 23 is formed on the surface, and a polycrystalline silicon film is further formed, and then the polycrystalline silicon film is etched away by reactive sputter etching. , which stopped at the position of the oxide film 23 and the stepped portion 2
2, polycrystalline silicon 24' is formed.
同図ｂはａの状態の試料にさらに反応性スパツ
タエツチングを行なつたものである。反応性ガス
のプラズマ２８を試料にほぼ垂直入射させ、多結
晶シリコン２４′のみならず、段部上面の酸化膜
２３−１及び段部下面の酸化膜２３−２もエツチ
ングすることになる。 Figure b shows the sample in state a further subjected to reactive sputter etching. The reactive gas plasma 28 is made almost perpendicularly incident on the sample, etching not only the polycrystalline silicon 24' but also the oxide film 23-1 on the upper surface of the step and the oxide film 23-2 on the lower surface of the step.
同図ｃは、図ａの試料を一定時間反応性スパツ
タエツチングし多結晶シリコン２４′が段部の高
さの約半分程度になつたときエツチングを停止し
た状態である。多結晶シリコンを段差の半分程度
の高さに形成し、段差を小さくしてやれば、他の
被膜あるいは、配線等が段差部分を横断する際に
段部で断線することが防止できる。 Figure c shows a state in which the sample in Figure a was subjected to reactive sputter etching for a certain period of time, and the etching was stopped when the polycrystalline silicon 24' reached about half the height of the step. By forming polycrystalline silicon to a height of about half the height of the step to make the step smaller, it is possible to prevent wire breakage at the step when other films, wiring, etc. cross the step.
第６図は、本発明の一実施例の走査型電子顕微
鏡写真である。写真中、半導体基板は２１であ
り、酸化膜は２３である。さらに段部側面および
その近傍のみを覆う如く形成された多結晶シリコ
ンは２４′で示している。この写真は、酸化膜２
３上の多結晶シリコンのエツチング除去を第３図
の時刻t3で停止したものに対応している。 FIG. 6 is a scanning electron micrograph of one embodiment of the present invention. In the photograph, the semiconductor substrate is 21 and the oxide film is 23. Furthermore, the polycrystalline silicon formed to cover only the side surface of the stepped portion and its vicinity is indicated by 24'. This photo shows oxide film 2
This corresponds to the case where the etching removal of the polycrystalline silicon on No. 3 was stopped at time t3 in FIG.
第７図は、本発明の他の実施例の走査型電子顕
微鏡写真である。半導体基板２１に段部を形成し
た後全面に酸化膜をCVD法（気相成長法）によ
り成長させ、段部側面およびその近傍のみを覆う
如く酸化膜２３′をドライエツチングで形成した
ものである。このエツチングは、反応性スパツタ
エツチング装置で、フレオン１４（CF4）ガスを
使用し装置のターゲツトして、テフロン樹脂を使
用し酸化膜の選択エツチを行なつたものである。
なお、この写真では、基板２１の段差と酸化膜２
３′の高さが一致していないが、これは、第３図
の時刻t3をやや上回る如くエツチング時間を選ん
だためである。 FIG. 7 is a scanning electron micrograph of another embodiment of the present invention. After forming a step on a semiconductor substrate 21, an oxide film is grown on the entire surface by CVD (vapor phase growth), and an oxide film 23' is formed by dry etching so as to cover only the side surface of the step and its vicinity. . This etching was carried out using a reactive sputter etching apparatus, using Freon 14 (CF 4 ) gas as a target of the apparatus, and selectively etching the oxide film using Teflon resin.
Note that this photo shows the difference in level of the substrate 21 and the oxide film 2.
The heights of 3' do not match, but this is because the etching time was selected to be slightly longer than time t3 in FIG.
以上の実施例ではドライエツチングとして主に
反応性スパツタエツチングについて述べたが、既
に明らかな如く、これに限定されることなく基板
表面にほぼ垂直にガスを入射せしめうるものであ
ればよい。 In the above embodiments, reactive sputter etching has been mainly described as dry etching, but as is already clear, the present invention is not limited to this, and any method may be used as long as it allows gas to be incident almost perpendicularly to the substrate surface.
また、基板そのものをエツチして段部を形成す
る場合について述べたが、これに限定される事な
く半導体基板上に形成される各種被膜の任意の形
状の段部に於ても適用されるものである。さら
に、本発明の方法はくり返し用いることができる
とともに、段部上面および底部に被膜はごく薄く
残存してもよい。 In addition, although we have described the case where the stepped portion is formed by etching the substrate itself, the present invention is not limited to this, but can also be applied to stepped portions of any shape in various films formed on semiconductor substrates. It is. Further, the method of the present invention can be used repeatedly, and a very thin coating may remain on the top and bottom of the step.
以上の実施例の説明から明らかな如く、本発明
によれば次の如き効果が得られる。 As is clear from the above description of the embodiments, the following effects can be obtained according to the present invention.
(1) 段部側面及びその近傍のみを覆う如く被膜が
形成される。(1) A film is formed so as to cover only the side surface of the stepped portion and its vicinity.
(2) その被膜の堆積時の膜厚に依存しているので
膜の堆積速度を制御することにより高精度に制
御され、かつ被膜の種類を任意に選択すること
ができ、単一被膜のエツチング条件の制御によ
つて任意の被膜の精密なサブミクロンの微細パ
ターンが得られる。(2) Since it depends on the thickness of the film at the time of deposition, it can be controlled with high precision by controlling the film deposition rate, and the type of film can be arbitrarily selected, making it possible to etch a single film. By controlling the conditions, precise submicron patterns of arbitrary coatings can be obtained.
(3) その被膜の高さは、エツチング時間により制
御し得るので、段部を所望の形状、例えば階段
状になし実効的に段部の高さを減少せしめ得
る。(3) Since the height of the coating can be controlled by the etching time, the height of the step can be effectively reduced by forming the step into a desired shape, for example, step-like.
(4) 写真蝕刻法によらず自己整合的な方法であ
り、しかも被膜の堆積形成とそのエツチングと
いう極めて簡単かつ制御性の良い方法である。(4) It is a self-aligning method that does not rely on photoetching, and is an extremely simple method with good controllability, consisting of depositing a film and etching it.
(5) 段部上の被膜のエツチングが半導体基板表面
に対して垂直方向に進行するので、半導体基板
の回転によつて影響を受けない。すなわち、段
部がどの様な方向へ形成されていてもその側面
に沿つて被膜の微細パターンが形成されるので
半導体装置のパターン設計の自由度が大きい。
以上の事から本発明は半導体装置全般に広範囲
に適用可能でありその特性および製造方法の改
善に大きく寄与するものである。(5) Since the etching of the film on the stepped portion proceeds in a direction perpendicular to the surface of the semiconductor substrate, it is not affected by the rotation of the semiconductor substrate. That is, no matter what direction the stepped portion is formed, a fine pattern of the film is formed along the side surface thereof, so there is a great degree of freedom in pattern design of the semiconductor device.
From the above, the present invention can be widely applied to semiconductor devices in general, and greatly contributes to improving their characteristics and manufacturing methods.
第１図ａ〜ｇは微細パターン形成法の従来の一
例の工程図、第２図ａ〜ｌは本発明による微細パ
ターン形成方法の一実施例の工程図、第３図は本
発明における反応性スパツタエツチングの進行状
態を示す説明図、第４図は本発明に使用した反応
性スパツタエツチ装置の概略図、第５図ａ〜ｃは
本発明による微細パターンの形成方法の他の実施
例の工程図、第６図は本発明の一実施例における
走査型電子顕微鏡による断面写真、第７図は本発
明の他の実施例の走査型電子顕微鏡による断面写
真である。
２１……半導体基板、２２……段部、２３，２
３′……酸化膜、２５……上面、２６……側面、
２７……底面、２４，２４′……多結晶シリコン
膜、２８……エツチングガス。
1A to 1G are process diagrams of a conventional example of a fine pattern forming method, FIGS. 2A to 1 are process diagrams of an embodiment of a fine pattern formation method according to the present invention, and FIG. An explanatory diagram showing the progress of sputter etching, FIG. 4 is a schematic diagram of the reactive sputter etching apparatus used in the present invention, and FIGS. 5 a to 5 c show steps of another embodiment of the method for forming fine patterns according to the present invention. 6 is a cross-sectional photograph taken using a scanning electron microscope according to one embodiment of the present invention, and FIG. 7 is a cross-sectional photograph taken using a scanning electron microscope according to another embodiment of the present invention. 21...Semiconductor substrate, 22...Step part, 23,2
3′...Oxide film, 25...Top surface, 26...Side surface,
27... Bottom surface, 24, 24'... Polycrystalline silicon film, 28... Etching gas.
Claims (1)
面および側面に連続した同一組成の堆積被膜を形
成せしめた後、エツチングガスを上記基板表面に
ほぼ垂直に入射せしめて上記被膜のドライエツチ
ングを行ない上記段部の上面および底面の上記被
膜を除去し上記段部の側面およびその近傍のみを
覆う如く上記被膜よりなるパターンを形成する事
を特徴とする半導体装置の製造方法。 ２ 被膜のエツチングガスとして、反応性ガスを
使用し、電界により基板表面にほぼ垂直に上記ガ
スを入射せしめ上記被膜のドライエツチングを行
う事を特徴とする特許請求の範囲第１項に記載の
半導体装置の製造方法。 ３ 被膜を形成せしめる際、段部の上面・底面お
よび側面における被膜の形成速度がほぼ等しい方
法を用いる事を特徴とする特許請求の範囲第１項
に記載の半導体装置の製造方法。 ４ 被膜のドライエツチングを行なつて基板段部
の側面およびその近傍のみに上記被膜を形成する
に際し、上記基板段部の高さのほぼ半分のみを覆
う如く上記被膜を除去して上記基板段部の断面形
状を階段状になす事を特徴とする特許請求の範囲
第１項に記載の半導体装置の製造方法。 ５ 基板表面に被膜と別の膜が形成されてなる特
許請求の範囲第１項に記載の半導体装置の製造方
法。[Claims] 1. After forming a continuous deposited film of the same composition on the top, bottom and side surfaces of a step formed on the surface of a semiconductor substrate, an etching gas is made to enter the substrate surface almost perpendicularly to the surface of the step. A method for manufacturing a semiconductor device, which comprises dry etching the film to remove the film on the top and bottom surfaces of the stepped portion and form a pattern of the film so as to cover only the side surface of the stepped portion and its vicinity. 2. The semiconductor according to claim 1, wherein a reactive gas is used as the etching gas for the film, and the gas is caused to be incident almost perpendicularly to the substrate surface by an electric field to dry-etch the film. Method of manufacturing the device. 3. The method of manufacturing a semiconductor device according to claim 1, characterized in that when forming the film, a method is used in which the film is formed at approximately the same speed on the top, bottom, and side surfaces of the stepped portion. 4. When dry etching the film to form the film only on the side surface of the substrate step and its vicinity, remove the film so as to cover only about half of the height of the substrate step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the cross-sectional shape of the semiconductor device is stepped. 5. The method of manufacturing a semiconductor device according to claim 1, wherein a film and another film are formed on the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11070377A JPS5444477A (en) | 1977-09-14 | 1977-09-14 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11070377A JPS5444477A (en) | 1977-09-14 | 1977-09-14 | Manufacture for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5444477A JPS5444477A (en) | 1979-04-07 |
| JPS6143847B2 true JPS6143847B2 (en) | 1986-09-30 |
Family
ID=14542306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11070377A Granted JPS5444477A (en) | 1977-09-14 | 1977-09-14 | Manufacture for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5444477A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS639848U (en) * | 1986-07-02 | 1988-01-22 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4234362A (en) * | 1978-11-03 | 1980-11-18 | International Business Machines Corporation | Method for forming an insulator between layers of conductive material |
| JPS57112028A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| EP2692514B1 (en) | 2012-07-31 | 2019-06-26 | Wincor Nixdorf International GmbH | Compacting device and method for compacting containers |
-
1977
- 1977-09-14 JP JP11070377A patent/JPS5444477A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS639848U (en) * | 1986-07-02 | 1988-01-22 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5444477A (en) | 1979-04-07 |
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