JPH0586659B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a processing technology for a width of 1 μm or less, and further relates to a method for manufacturing a fine, high-density LSI using this method.

(Prior art) The effect of fine pattern formation technology on increasing the scale of LSI is extremely large. Regarding exposure methods, various methods have been developed, such as ultraviolet, far ultraviolet, reduction projection, electron beam, ion beam, and X-ray. Advances in these techniques have made it possible to form submicron patterns, but these techniques also have the following problems. In other words, the performance of ultraviolet, far ultraviolet, and reduction projection exposure has all improved based on the progress and track record of existing equipment, but in terms of resolution, the limit is expected to be 0.7 to 1 μm. Pattern formation below this value is possible by electron beam, X-ray, and ion beam exposure methods. However, with electron beam exposure, there is a decrease in throughput, with ion beam exposure, the effects of devices are unknown, and with X-ray exposure,
There are problems with the stability and strength of the line mask substrate, and the high resolution of each exposure method is not yet fully utilized. As described above, in conventional pattern forming methods, there has been no pattern forming technique that can form submicron patterns and that can be easily applied to the LSI level.

As another method for forming submicron patterns, various attempts have been made to utilize side etching of deposited films, but there are problems with side etching uniformity and controllability, and this also applies to LSI.
There was no method that could be easily applied to this level.

(Object of the invention) In order to eliminate these drawbacks, the present invention applies a directional film deposition method to a method for forming fine patterns. The aim is to make processing easier and thereby increase the density and speed of LSI.

(Structure of the Invention) In order to achieve the above-mentioned object, the present invention deposits a first material on a substrate and then forms a pattern thereon,
A second material, which is a compound, is deposited on the entire surface by ECR-type plasma CVD, which is a chemical vapor deposition method using directional plasma, and the pattern of the first material is formed by etching. By removing the second material attached around the edge, a groove is formed by the first material and the second material so that the exposed surface of the substrate can be seen from above the substrate surface in a direction perpendicular to the substrate surface. The present invention provides a method for manufacturing a semiconductor device, characterized in that the exposed substrate material in the groove portion is subjected to directional etching using the patterned first material and the second material as a mask. That is.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

Figure 1A and B show a directional film deposition method;
This figure shows the change in shape when SiO ₂ is deposited on a base with steps using the ECR plasma deposition method and then etched. Figure 1A shows RIE using SiO ₂ , etc. patterned in advance on Si1 as a mask.
(reactive ion etching)
This is the cross-sectional structure of a sample in which Si was etched to form a groove in the Si, and then a SiO ₂ film 2 was deposited thereon by ECR-type plasma deposition. The RIE conditions were CBrF ₃ used as gas, 0.03 Torr, 200 W, and the depth of the Si groove was 1 μm. Furthermore, the widths of the concave and convex portions of the Si groove are both 1 μm. The deposited film thickness of SiO ₂ by ECR type plasma deposition method was 0.5 μm, and the deposition conditions were
SiH ₄ (100%) 10c.c./min, O ₂ 10c.c./min, 2×
10 ^-4 Torr, 100W. When these are light-etched, the SiO ₂ film deposited on the side walls of the Si groove is rapidly etched away due to the high etching rate, resulting in the structure shown in FIG. 1B. 3,4
indicates the remaining SiO ₂ film. ECR type plasma that generates plasma using electron cyclotron resonance
In the CVD method, the gas pressure for depositing the film is one to two orders of magnitude lower than that in the conventional plasma CVD method.
The film is formed by forming a plasma flow using a diverging magnetic field and irradiating the plasma onto the substrate, so ions with strong directionality and moderate energy are irradiated onto the film surface. The ionization rate is also about an order of magnitude higher than that of conventional plasma CVD methods. In addition, the properties of the formed film are such that ECR is possible without substrate heating.
The etching rate of films formed by thermal CVD with buffered hydrofluoric acid is similar to that of films formed by thermal CVD.
It has the characteristic of being able to form films with far superior properties than the CVD method.

Figure 2 shows the light etching time and Figure 1B.
The relationship between the dimensions of each part shown in is shown below. The etching solution was a HF solution diluted with H ₂ O (50% HF60c.c., H ₂
O1940c.c.). When the etching time is 10 minutes at room temperature, the gap α _B between the SiO ₂ film and the Si side wall in the recess is 0.15 μm. It goes without saying that the size of this gap α _B can take various values by varying the thickness of the deposited SiO ₂ film and the composition of the HF liquid.

Figure 3 shows the light etching time and Figure 1B.
The relationship between angles α _B and α _T shown in is shown below. Even if the etching time is increased, α _B remains constant at approximately 70°. Therefore, the taper angle of the oxide film 4 in the recess shown in FIG. 1B is constant. Also, the taper angle of the oxide film 3 on the convex portion is approximately
It becomes constant at 100°.

Here, as a specific example, Si is used as a substrate with a step on the base, but if the surface has a step,
Materials other than Si, such as semiconductor materials such as InP and GaAs, or metal materials such as Al and Mo, Al ₂ O ₃ , Si ₃
It goes without saying that the same tendency occurs with insulators such as _N4 . Also, although SiO ₂ was shown as the deposited film,
The same applies to any film that can be formed by ECR type plasma deposition, such as a Si ₃ N ₄ film or a Si _X N _Y O _Z film.

By using the properties explained using FIGS. 1 to 3, it becomes possible to process fine grooves. Figure 4 A-E,
Examples thereof will be described in FIGS. 5A to 5C.

FIG. 4 shows that after forming an oxide film 5 on a silicon substrate 1 by thermal oxidation or CVD, a polysilicon film 6 is formed on this, a resist film 7 is further patterned on top of this, and then SiO ₂ shows a structure in which two films 8 are deposited by ECR type plasma deposition method. For example, the thickness of each film is 0.5 μm for polysilicon film 6, and 0.5 μm for resist film 7.
is 1 μm, and the SiO ₂ film 8 is 0.5 μm. This is light etched to obtain the structure shown in FIG. 4B. 9,
10 shows the SiO ₂ film left after etching.
When etching was performed for 14 minutes using the diluted HF solution explained in FIG. 2, the size of the gap a shown in FIG. 4B was 0.2 μm, and the thickness of both SiO ₂ films 9 and 10 was 0.2 μm.
becomes. For example, RIE using CBrF ₃ gas
If etching is performed, the structure shown in FIG. 4C is obtained. Since the etching rate ratio of Si and SiO ₂ by this RIE is about 8 times, the SiO ₂ film 10 can sufficiently serve as a mask. The thickness of the SiO ₂ film 10 in FIG. 4C is approximately 0.14 μm. Furthermore, since the etching rate ratio between Si and resist is approximately three times, the resist film 7 can also serve as a sufficient mask. The groove b shown in FIG. 4C is wider than the groove a in FIG. 4B because both the resist film 7 and the SiO ₂ film 10 are etched by RIE. At this time, the gap between grooves b is approximately 0.35 μm. 11 and 12 indicate SiO ₂ films. Next, the SiO ₂ film 12 is removed to obtain the image shown in FIG. 4D, and the resist film 7 is further removed to obtain the image shown in FIG. 4E.
However, in this case, the polysilicon base 5 is SiO ₂
Since it is a film, when removing the SiO ₂ film 12 used as a mask, the SiO ₂ film 5 also has a gap of about 0.15 μm.
Etched. This is shown as c in FIG. 4D. In the above embodiment, an example using a silicon substrate has been described as 1, but a semiconductor or other substrate can be used in addition to this. Also, instead of the silicon oxide film 5, an insulator is used, and instead of the polysilicon 6, silicon-containing Al, Mo-Si, or
Si ₃ N ₄ may be used instead of the SiO ₂ film 8, and Si ₃ N ₄ may be used instead of the resist 7.

A process for preventing etching of the underlying SiO ₂ film is shown in FIGS. 5A to 5C. After proceeding to the step shown in FIG. 4B, the etching of the polysilicon 6 is stopped without etching until it finally comes out as shown in FIG. 5A. Thereafter, the SiO ₂ films 13 and 14 and the resist film 7 are removed to obtain the structure shown in FIG. 5B. The entire surface is etched using RIE, for example, to obtain the image shown in FIG. 5C. The examples shown in FIGS. 4 and 5 can be widely applied to cutting conductor wiring or materials such as insulators with minute gaps of 1 μm or less.

Although RIE was used for etching in the above embodiments, it is of course possible to use wet etching if necessary.

6A to 6F show a manufacturing method in which a groove e is formed in the Si substrate 1 and a film of poly-Si or SiO ₂ is filled in the groove. This is a manufacturing method suitable for obtaining a fine isolation structure between elements. Thermal oxide film 1 on Si substrate 1
After forming a resist pattern 16, a SiO ₂ film 17 is deposited on the entire surface by a directional film deposition method such as ECR type plasma deposition method to obtain the structure shown in FIG. 6A. The thickness of the thermal oxide film 15 is, for example, 500 Å,
The thickness of the resist 16 is 1 to 1.5 μm, and the thickness of the SiO ₂ film 17 is 1 μm. Etching was performed for 14 minutes using the diluted HF described in FIG. 2 to obtain the structure shown in FIG. 6B. The interval d is 0.2 μm, and the SiO ₂ films 18 and 19
The film thickness is 0.7μm. Using the SiO ₂ films 18, 19 and the resist 16 as masks, the Si substrate 1 is etched by RIE using CBrF ₃ gas to obtain the structure shown in FIG. 6C. When the depth of the Si groove e is 1.5 μm, the width of the upper end of the groove e increases to about 0.4 to 0.6 μm because the SiO ₂ films 20 and 21 and the resist film 16 are etched. The lower end of the groove e is 0.2 to 0.3 μm. SiO ₂ film 2
0, 21, remove the resist film 16, and then
After removing the SiO ₂ film 15, the Si substrate 1 is cleaned and a thermal oxide film 22 is formed to obtain the structure shown in FIG. 6D. A SiO ₂ film or a poly-Si film is deposited on this to obtain the structure shown in FIG. 6E. The thickness of this deposited film 23 is approximately 0.5 to 1 μm. The structure shown in FIG. 6F is obtained by etching this again by RIE, or by applying a resist and etching by RIE. In this structure, the width of the thin films 22 and 23 embedded in the Si substrate 1 is 0.4 to 0.6 μm and the depth is 1.5 μm, which is suitable as a fine element isolation structure. Of course, the conditions described above are just one specific example, and it goes without saying that by changing the conditions, element isolation structures having various dimensions can be manufactured. It goes without saying that the resist 16 may be replaced by a patterned SiO ₂ film.

FIGS. 7A to 7I show other examples of manufacturing isolation structures using the method for forming fine grooves according to the present invention. In FIG. 7A, a thermal oxide film 24 is formed on the Si substrate 1, a heat-resistant CVDSi ₃ N ₄ film 25 is formed thereon, and a resist pattern 26 is further formed. The film thickness of 24 is 500 Å, the film thickness of 25 is 1000 Å, and the film thickness of 26 is 1
~1.5μm. A SiO ₂ film 27 is deposited thereon by a directional film deposition method using the ECR type plasma deposition method to obtain the structure shown in FIG. 7B. This is diluted as shown in Figure 2.
Etching is performed using HF for 14 minutes, and the Si ₃ N ₄ film 25, SiO ₂ film 24, and Si substrate 1 are etched by the aforementioned RIE using CBrF ₃ to obtain the image shown in FIG. 7C. The depth of the groove f is approximately 1 μm. The SiO ₂ films 28 and 29 are removed to obtain FIG. 7D. Using resist 26 as a mask
The Si ₃ N ₄ film 25 and the SiO ₂ film 24 are etched, and the Si substrate 1 is further etched by about 1 μm to obtain the image shown in FIG. 7E. At this time, the width of the groove g is 0.4 to 0.6 μm. After removing the resist 26, a thermal oxide film 30 with a thickness of 200 to 300 Å is formed, and then a CVDSi ₃ N ₄ film 31 is formed on the entire surface.
After depositing 0.3 μm, the image shown in FIG. 7F is obtained. This is etched using RIE to obtain Figure 7G. Si ₃ N ₄ films 25 and 3
Selective oxidation is performed using No. 1 as a mask to obtain FIG. 7H. 32 indicates an oxide film. The Si ₃ N ₄ film 25 and the oxide film 24 are removed to obtain the structure shown in FIG. 7I. As explained above, the field region is formed in self-alignment with respect to the element region. The thickness of the oxide film 32 is
2 μm, the width of the Si ₃ N ₄ film 31 is about 0.4 to 0.6 μm,
Suitable for fine isolation between elements. Furthermore, it goes without saying that a patterned SiO ₂ film can be used instead of the resist pattern 26.

FIGS. 8A to 8F are fabrication examples of other element isolation structures according to the present invention. In the structure shown in FIG. 7C, the resist 26 and the SiO ₂ film 28 deposited thereon are removed by lift-off to obtain the structure shown in FIG. 8A.
Si ₃ N ₄ film 25, SiO ₂ film 2 by RIE etching
4. Etch the Si substrate 1 to obtain the image shown in FIG. 8B.
A CVDSi ₃ N ₄ film 34 is deposited on this to a thickness of 0.3 μm to obtain the image shown in FIG. 8C. 8D by RIE etching, FIG. 8E by thermal oxidation, and Si ₃ N ₄
By removing the film 25 and the thermal oxide film 24, FIG. 8F is obtained. Also in this method described above, the field region is formed in self-alignment with respect to the element region. Like FIG. 7I, this is also suitable for a fine isolation structure between elements.

As explained above, according to the present invention, a fine pattern of about 0.1 to 0.5 μm can be formed by using a directional film deposition method and an ECR type plasma deposition method. Using this formation method, it is possible to easily manufacture a fine device isolation structure in LSI that satisfies self-alignment with respect to the device region.

Further, although CVDSi ₃ N ₄ film is used as the oxidation-resistant material in the above embodiment, it is of course possible to use other oxidation-resistant materials such as Al ₂ O ₃ .

(Effects of the Invention) As described above, according to the present invention, a first material is deposited on a substrate, a pattern is formed on the first material, and a chemical vapor deposition method using directional plasma is applied on the first material. By depositing a second material, which is a compound, on the entire surface by etching and removing the second material attached around the edge of the pattern of the first material by etching, the substrate surface is etched from above the substrate surface. A groove is formed by the first material and the second material so that the exposed surface of the substrate can be seen in the direction perpendicular to the patterned first material.
By performing directional etching using the material and the second material as a mask, (a) the dimensional accuracy of the groove width formed by etching is good, that is, according to the present invention;
Grooves with a width of about 0.1 to 0.5 μm can be easily machined, so in LSI, shapes that require cutting of materials such as conductor wiring or insulating films can be manufactured, especially with gaps of about 0.1 to 0.5 μm (ROW). ) Another application example is that if applied to element isolation, it is possible to fabricate a fine element isolation structure (c) The process is simplified and there is no deterioration in performance due to mask material adhesion during the etching process. It is something.

[Brief explanation of the drawing]

Figures 1A and B show changes in shape when etching a thin film using a directional film deposition method, Figures 2 and 3 show the etching time dependence of the shape shown in Figure 1, and Figure 4A. ~E, Figures 5A to C show a method for forming fine grooves using the deposited film shown in Figure 1, and Figure 6A
-F, FIGS. 7A-I, and 8A-F show a method of manufacturing a fine isolation structure using the fine groove forming method shown in FIGS. 1-5. 1... Si substrate, 2, 3, 4... Thin film formed by directional film deposition method, 5... SiO ₂ film,
6... Poly-Si film, 7... Resist film, 8, 9, 1
0, 11, 12, 13, 14... Thin film formed by directional film deposition method, 15, 22, 2
4, 30, 33... thermal oxide film, 16, 26... resist film or SiO ₂ film, 17, 18, 19, 20,
21, 27, 28, 29... Thin film formed by directional film deposition method, 23... CVDSiO ₂
film or CVD poly-Si film, 25, 31, 34... film of oxidation-resistant material, 32, 35... thermal oxidation film.

Claims (1)

[Claims] 1. After depositing a first material on a substrate, a pattern is formed on the first material, and an ECR type plasma which is a chemical vapor deposition method using directional plasma is applied.
A second material, which is a compound, is deposited on the entire surface by the CVD method, and by etching, the fragile filmy parts of the second material attached around the edges of the pattern of the first material are removed, and the flat surface is By leaving the second material made of a deposited dense film, the first material and the second material are combined so that the exposed surface of the substrate can be seen from above the substrate surface in a direction perpendicular to the substrate surface. and forming a deep groove by directional etching the exposed substrate material in the groove portion using the patterned first material and the second material as a mask. A method for manufacturing a semiconductor device. 2. In the method for manufacturing a semiconductor device according to claim 1, an element isolation structure having a flat surface and an isolation width of 1 μm or less is obtained by filling the deep groove with a film deposited by CVD or the like. A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device. 3. In the method of manufacturing a semiconductor device according to claim 1, the deep groove is filled with a deposited film of an oxidation-resistant material, and the element region is also covered with the film of the oxidation-resistant material, and after selective oxidation, The substrate surface is not coated with the oxidation-resistant material film so that it is flat.
1. A method of manufacturing a semiconductor device, which comprises etching a Si region to adjust the height difference, and then performing selective oxidation to obtain a selective oxide film with a flat surface.