KR100523627B1 - Method for forming inter-dielectric layer of semiconductor device - Google Patents

Method for forming inter-dielectric layer of semiconductor device Download PDF

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KR100523627B1
KR100523627B1 KR10-2003-0053425A KR20030053425A KR100523627B1 KR 100523627 B1 KR100523627 B1 KR 100523627B1 KR 20030053425 A KR20030053425 A KR 20030053425A KR 100523627 B1 KR100523627 B1 KR 100523627B1
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film
interlayer insulating
insulating film
bpsg
forming
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KR10-2003-0053425A
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KR20050014985A (en
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김승현
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 BPSG 막의 크리스탈 디펙트를 차단함과 동시에 어닐링 공정시에 목표로 하는 리플로우 특성을 얻을 수 있도록 한다는 것으로, 이를 위하여 본 발명은, 층간 절연막인 BPSG을 증착할 때 BPSG 막 표면의 B, P 농도를 감소시키거나 혹은 BPSG 막 위에 USG막을 올려주는 종래 방법과는 달리, B, P 도펀트 분위기에서 어닐링 공정을 수행하여 BPSG 막 또는 USG 막 표면의 B, P 농도를 증가시켜 줌으로써 후속하는 BPSG 어닐링 공정시에 목표로 하는 리플로우 특성을 얻을 수 있는 것이다.The present invention is to block the crystal defect of the BPSG film and at the same time to achieve the desired reflow characteristics during the annealing process, the present invention, when depositing BPSG as an interlayer insulating film, B, Unlike the conventional method of reducing the P concentration or placing a USG film on the BPSG film, the annealing process is performed in the B and P dopant atmosphere to increase the B and P concentrations on the surface of the BPSG film or USG film, thereby subsequent BPSG annealing. It is possible to obtain target reflow characteristics during the process.

Description

반도체 소자의 층간 절연막 형성 방법{METHOD FOR FORMING INTER-DIELECTRIC LAYER OF SEMICONDUCTOR DEVICE}METHODS FOR FORMING INTER-DIELECTRIC LAYER OF SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 층간 절연막을 형성하는데 적합한 반도체 소자 제조 기법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device manufacturing technique suitable for forming an interlayer insulating film of a semiconductor device.

잘 알려진 바와 같이, 반도체 소자는 기판 상에 다수의 층이 순차 적층되는 구조를 갖는데, 다층 구조에서 각 층간의 전기적인 절연 등을 위해 층간 절연막이 필요하며, 이러한 층간 절연막으로는 BPSG 등이 주로 이용되고 있다.As is well known, a semiconductor device has a structure in which a plurality of layers are sequentially stacked on a substrate, and an interlayer insulating film is required for electrical insulation between the layers in a multilayer structure, and BPSG or the like is mainly used as the interlayer insulating film. It is becoming.

종래 방법에 따라 층간 절연막인 BPSG 막을 기판 상에 증착할 경우 과도한 B, P 등의 도펀트가 유입되어 고농도의 BPSG 막으로 될 경우가 발생할 수 있는데, 이 경우 BPSG 막의 표면에서 대기중의 수분과 반응하여 BPSG 막의 표면에 H3BO4, H3PO4 등의 화합물이 형성된다.When the BPSG film, which is an interlayer insulating film, is deposited on a substrate according to the conventional method, excessive dopants such as B and P may flow into the BPSG film at a high concentration. Compounds such as H 3 BO 4 and H 3 PO 4 are formed on the surface of the BPSG film.

이와 같이 BPSG 막의 표면에 화합물이 형성되는 경우 후속하는 어닐링 공정시에 BPO4의 크리스탈 디펙트(crystal defect)가 형성되는 문제가 발생하게 되는데, 이를 방지하기 위하여 종래에는 BPSG 증착시에 BPSG 표면의 B, P 농도를 감소시키거나 혹은 BPSG 막 위에 USG를 증착하여 BPSG 막과 대기의 수분이 접촉하는 것을 막는 등의 방법을 이용하고 있다.As such, when a compound is formed on the surface of the BPSG film, a problem occurs in that a crystal defect of BPO 4 is formed in a subsequent annealing process. For example, a method of reducing the P concentration or depositing USG on the BPSG film to prevent the BPSG film from contacting with moisture in the air is used.

그러나, 상기한 바와 같이 B, P 농도를 감소시키거나 혹은 BPSG 막 위에 USG(undoped SiO2)를 증착하는 종래 방법의 경우 후속하는 어닐링 공정시에 원하는 리플로우(reflow) 특성을 얻기가 어렵다는 문제점을 갖는다.However, as described above, the conventional method of reducing the B, P concentration or depositing USG (undoped SiO 2 ) on the BPSG film has a problem that it is difficult to obtain desired reflow characteristics in a subsequent annealing process. Have

따라서, 본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로, BPSG 막의 크리스탈 디펙트를 차단함과 동시에 어닐링 공정시에 목표로 하는 리플로우 특성을 얻을 수 있는 반도체 소자의 층간 절연막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and provides a method for forming an interlayer insulating film of a semiconductor device capable of blocking crystal defects of a BPSG film and attaining a desired reflow characteristic during an annealing process. Its purpose is to.

상기 목적을 달성하기 위하여 본 발명은, 임의의 패턴의 금속 배선을 갖는 반도체 소자에 층간 절연막을 형성하는 방법에 있어서, 반도체 기판 상에 상기 금속 배선을 형성하는 과정과, 상기 반도체 기판의 전면에 후막의 층간 절연막을 형성하는 과정과, 상기 층간 절연막의 상부에 박막의 차단막을 형성하는 과정과, B 및/또는 P 도펀트 분위기에서 어닐링 공정을 수행하여 상기 차단막의 표면에 B 및/또는 P의 농도를 증가시켜 주는 과정을 포함하는 반도체 소자의 층간 절연막 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film in a semiconductor device having a metal wiring of any pattern, the process of forming the metal wiring on a semiconductor substrate, and a thick film on the entire surface of the semiconductor substrate Forming an interlayer insulating film, forming a thin film blocking film on the interlayer insulating film, and performing an annealing process in a B and / or P dopant atmosphere to form a concentration of B and / or P on the surface of the blocking film. It provides a method for forming an interlayer insulating film of a semiconductor device comprising a step of increasing.

본 발명의 상기 및 기타 목적과 여러 가지 장점은 이 기술분야에 숙련된 사람들에 의해 첨부된 도면을 참조하여 하기에 기술되는 본 발명의 바람직한 실시 예로부터 더욱 명확하게 될 것이다.The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

이하 첨부된 도면을 참조하여 본 고안의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 핵심 기술요지는, 층간 절연막인 BPSG을 증착할 때 BPSG 막 표면의 B, P 농도를 감소시키거나 혹은 BPSG 막 위에 USG막을 올려주는 전술한 종래 방법과는 달리, B, P 도펀트 분위기에서 어닐링 공정을 수행하여 BPSG 막 또는 USG 막 표면의 B, P 농도를 증가시켜 줌으로써 어닐링 공정시에 목표로 하는 리플로우 특성을 얻을 수 있도록 한다는 것으로, 이러한 기술적 수단을 통해 본 발명에서 목적으로 하는 바를 쉽게 달성할 수 있다.A key technical aspect of the present invention is to reduce the B, P concentration on the surface of the BPSG film when depositing BPSG, which is an interlayer insulating film, or to increase the USG film on the BPSG film. By performing the annealing process to increase the B and P concentrations on the surface of the BPSG film or USG film, it is possible to obtain the desired reflow characteristics during the annealing process. Can be achieved.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a, 1b 및 1c는 본 발명의 바람직한 실시 예에 따라 반도체 소자의 층간 절연막을 형성하는 과정을 도시한 공정 순서도이다.1A, 1B, and 1C are flowcharts illustrating a process of forming an interlayer insulating film of a semiconductor device according to a preferred embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(102) 상에 스퍼터링 등의 방법을 이용하여 알루미늄 등의 금속 물질을 형성하고, 그 위에 스핀 코팅 등의 방법으로 포토레지스트 물질을 형성한 후 노광, 현상 등의 공정을 수행함으로써, 금속 물질의 상부에 임의의 패턴을 갖는 식각 마스크를 형성한다.Referring to FIG. 1A, a metal material such as aluminum is formed on a semiconductor substrate 102 using a method such as sputtering, and a photoresist material is formed thereon by a method such as spin coating, followed by exposure or development. By performing the above, an etching mask having an arbitrary pattern is formed on the metal material.

이어서, 반응성 이온 식각(RIE) 등의 공정을 이용하는 식각 공정을 수행하여 금속 물질의 일부를 선택적으로 식각한 후 잔류하는 식각 마스크를 제거함으로써 반도체 기판(102) 상에 임의의 패턴을 갖는 금속 배선(예를 들면, 게이트 전극 등)(104)을 형성한다.Subsequently, by performing an etching process using a process such as reactive ion etching (RIE) to selectively etch a part of the metal material and removing the remaining etching mask, the metal wiring having an arbitrary pattern on the semiconductor substrate 102 ( For example, a gate electrode or the like 104 is formed.

다음에, 증착 공정을 수행함으로써, 일 예로서 도 1b에 도시된 바와 같이, 금속 배선(104)이 형성된 반도체 기판(102)의 전면에 후막의 층간 절연막(106)을 형성한다. 여기에서, 층간 절연막(106)으로는 저농도 BPSG 막을 사용할 수 있다.Next, by performing the deposition process, as shown in FIG. 1B, the interlayer insulating film 106 of the thick film is formed on the entire surface of the semiconductor substrate 102 on which the metal wiring 104 is formed. Here, a low concentration BPSG film can be used as the interlayer insulating film 106.

다시, 증착 공정을 수행함으로써, 일 예로서 도 1c에 도시된 바와 같이, 층간 절연막(106)의 상부에 박막의 차단막(108)을 형성한다. 여기에서, 차단막(108)으로는 USG 막을 사용할 수 있다.Again, by performing the deposition process, as shown in FIG. 1C, a thin film blocking film 108 is formed on the interlayer insulating film 106. Here, the USG film may be used as the blocking film 108.

이어서, B, P 도펀트 분위기하에서 어닐링 공정을 수행하는데, 이러한 어닐링 공정시에 차단막(108)의 표면에 B, P의 농도가 증가하게 된다. 이와 같이 차단막(108)의 표면에 B, P의 농도를 증가시켜 주는 것은 후속하는 어닐링 공정시에 목표로 하는 리플로우 특성을 얻을 수 있도록 하기 위해서이다.Subsequently, an annealing process is performed in a B and P dopant atmosphere. In this annealing process, concentrations of B and P increase on the surface of the blocking film 108. In this way, the concentrations of B and P are increased on the surface of the blocking film 108 in order to obtain target reflow characteristics during the subsequent annealing process.

여기에서, B, P 도펀트 소오스로는 PH3 나 B2H6 등의 가스 소오스를 사용하거나 혹은 TEB(Triethyl Borate) 나 TMOP(Trimethyl Phosphate) 등의 액체 소오스를 사용할 수 있다.Here, as the B and P dopant source, a gas source such as PH 3 or B 2 H 6 may be used, or a liquid source such as TEB (Triethyl Borate) or TMOP (Trimethyl Phosphate) may be used.

한편, 본 발명의 바람직한 실시 예에서는 차단막 표면에서의 B, P 농도 증가를 위해 B, P 분위기에서 어닐링을 수행하는 것으로 하여 설명하였으나, 본 발명이 반드시 이에 한정되는 것은 아니며, 필요 또는 용도에 따라 B 또는 P 도펀트만을 증가시키는 방식으로 차단막의 표면을 처리할 수 있음은 몰론이다.Meanwhile, in the preferred embodiment of the present invention, annealing is performed in an atmosphere of B and P to increase the concentration of B and P on the surface of the barrier film. However, the present invention is not necessarily limited thereto and according to necessity or use, Alternatively, the surface of the barrier film can be treated in such a way as to increase only the P dopant.

또한, 본 발명에 따르면, B 및/또는 P 소오스의 가스량을 변화시킴으로써 리플로우 레이트를 제어할 수도 있다.In addition, according to the present invention, the reflow rate can be controlled by changing the gas amount of the B and / or P source.

이상 설명한 바와 같이 본 발명에 따르면, 층간 절연막인 BPSG을 증착할 때 BPSG 막 표면의 B, P 농도를 감소시키거나 혹은 BPSG 막 위에 USG막을 올려주는 전술한 종래 방법과는 달리, B, P 도펀트 분위기에서 어닐링 공정을 수행하여 BPSG 막 또는 USG 막 표면의 B, P 농도를 증가시켜 줌으로써, BPSG 막의 크리스탈 디펙트를 차단함과 동시에 후속하는 BPSG 어닐링 공정시에 목표로 하는 리플로우 특성을 얻을 수 있다.As described above, according to the present invention, unlike the above-described conventional method of reducing the B, P concentration on the surface of the BPSG film or placing the USG film on the BPSG film when depositing the BPSG, which is an interlayer insulating film, the B, P dopant atmosphere By increasing the B and P concentration on the surface of the BPSG film or USG film by performing an annealing process, the crystal defect of the BPSG film can be blocked and the target reflow characteristics can be obtained during the subsequent BPSG annealing process.

도 1a, 1b 및 1c는 본 발명의 바람직한 실시 예에 따라 반도체 소자의 층간 절연막을 형성하는 과정을 도시한 공정 순서도.1A, 1B and 1C are process flowcharts showing a process of forming an interlayer insulating film of a semiconductor device according to a preferred embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

102 : 반도체 기판 104 : 금속 배선102 semiconductor substrate 104 metal wiring

106 : 층간 절연막 108 : 차단막106: interlayer insulating film 108: blocking film

Claims (4)

임의의 패턴의 금속 배선을 갖는 반도체 소자에 층간 절연막을 형성하는 방법에 있어서,In the method for forming an interlayer insulating film in a semiconductor device having a metal wiring of any pattern, 반도체 기판 상에 상기 금속 배선을 형성하는 과정과,Forming the metal wiring on a semiconductor substrate; 상기 반도체 기판의 전면에 후막의 층간 절연막을 형성하는 과정과,Forming a thick interlayer insulating film on the entire surface of the semiconductor substrate; 상기 층간 절연막의 상부에 박막의 차단막을 형성하는 과정과,Forming a thin film blocking film on the interlayer insulating film; B 및/또는 P 도펀트 분위기에서 어닐링 공정을 수행하여 상기 차단막의 표면에 B 및/또는 P의 농도를 증가시켜 주는 과정A process of increasing the concentration of B and / or P on the surface of the barrier layer by performing an annealing process in a B and / or P dopant atmosphere. 을 포함하는 반도체 소자의 층간 절연막 형성 방법.Method for forming an interlayer insulating film of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 B 및/또는 P 도펀트 소오스는, PH3 또는 B2H6의 가스 소오스인 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.And said B and / or P dopant source is a gas source of PH 3 or B 2 H 6 . 제 1 항에 있어서,The method of claim 1, 상기 B 및/또는 P 도펀트 소오스는, TEB(Triethyl Borate) 또는 TMOP(Trimethyl Phosphate)의 액체 소오스인 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.The B and / or P dopant source is a liquid source of TEB (Triethyl Borate) or TMOP (Trimethyl Phosphate). 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 방법은, B 및/또는 P 소오스량을 변화시켜 상기 층간 절연막의 리플로우 레이트를 조절 가능한 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.The method is characterized in that the reflow rate of the interlayer insulating film can be adjusted by varying the amount of B and / or P source.
KR10-2003-0053425A 2003-08-01 2003-08-01 Method for forming inter-dielectric layer of semiconductor device KR100523627B1 (en)

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