KR100239731B1 - Method of forming inorganic layer during semiconductor manufacturing process - Google Patents

Method of forming inorganic layer during semiconductor manufacturing process Download PDF

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KR100239731B1
KR100239731B1 KR1019970019120A KR19970019120A KR100239731B1 KR 100239731 B1 KR100239731 B1 KR 100239731B1 KR 1019970019120 A KR1019970019120 A KR 1019970019120A KR 19970019120 A KR19970019120 A KR 19970019120A KR 100239731 B1 KR100239731 B1 KR 100239731B1
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layer
sog
forming
conductive layer
insulating layer
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KR19980083715A (en
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정석철
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김영환
현대반도체주식회사
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Priority to JP10128681A priority patent/JPH118233A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 제조공정에서의 무기층 형성방법에 관한 것으로, 반도체 기판상에 제 1 도전층패턴을 형성하는 공정과, 상기 제 1 도전층패턴을 포함한 반도체 기판상에 SOG층을 형성하는 공정과, 상기 SOG층을 오존(O3)분위기에서 열처리하는 공정과, 상기 SOG층상에 제 1 절연층을 형성하는 공정과, 상기 제 1 도전층패턴이 노출되도록 에칭하여 비아(via)를 형성하는 공정과, 상기 비아를 포함한 제 1 절연층상에 제 2 도전층패턴을 형성하는 공정을 포함하여 이루어지고, 상기한 바와 같은 본 발명에 의한 반도체 제조공정에서의 무기층형성방법은 에치백공정을 수행하지 않으므로 에치백시 문제시된 절연층/SOG층의 에칭선택비의 조절 및 공정상의 마진문제가 해결되어지고, 무기화된 SOG는 변화이전의 유기SOG의 초기평탄화상태를 그대로 유지할 수 있고, 무기화된 SOG로 인해 비아형성시 산소 플라즈마에 대한 저항력이 높아지는 효과가 있다.The present invention relates to a method for forming an inorganic layer in a semiconductor manufacturing process, comprising: forming a first conductive layer pattern on a semiconductor substrate; and forming a SOG layer on a semiconductor substrate including the first conductive layer pattern; And heat treating the SOG layer in an ozone (O 3 ) atmosphere, forming a first insulating layer on the SOG layer, and etching to expose the first conductive layer pattern to form vias. And forming a second conductive layer pattern on the first insulating layer including the via, wherein the inorganic layer forming method in the semiconductor manufacturing process according to the present invention as described above does not perform an etch back process. Therefore, the problem of controlling the etching selectivity of the insulating layer / SOG layer and the margin of the process, which are a problem during etch back, are solved, and the inorganicized SOG can maintain the initial leveling state of the organic SOG before the change. Inorganic SOG has the effect of increasing resistance to oxygen plasma during via formation.

Description

반도체 제조공정에서의 무기층 형성방법Inorganic layer formation method in semiconductor manufacturing process

본 발명은 반도체 소자의 층간절연층에 관한 것으로, 특히 메탈층간의 평탄화공정에 일반적으로 사용하는 유기물질층을 변화시켜 무기물질층을 형성하는 방법에 관한것이다.The present invention relates to an interlayer insulating layer of a semiconductor device, and more particularly, to a method of forming an inorganic material layer by changing an organic material layer generally used in the planarization process between metal layers.

종래의 평탄화공정에 SOG(Spin On Glass)가 널리 사용되어 왔다. 일반적으로 SOG는 탄소성분의 함유유무에 따라 탄소성분을 함유하는 유기SOG와 탄소성분을 함유하지 않은 무기SOG로 구별되어진다.In the conventional planarization process, SOG (Spin On Glass) has been widely used. In general, SOG is classified into organic SOG containing carbon component and inorganic SOG containing no carbon component depending on the presence or absence of carbon component.

우선, 무기SOG를 이용한 종래 메탈층간의 평탄화공정에 대해 첨부된 도면, 도 1a∼1f를 참조하여 설명하기로 한다.First, a planarization process between conventional metal layers using inorganic SOG will be described with reference to the accompanying drawings and FIGS. 1A to 1F.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(1)상에 기저층(bottom layer)(2)을 형성하고, 상기 기저층(2)상에 제 1 도전층패턴(4)을 형성하고, 상기 제 1 도전층패턴(4)을 포함한 상기 반도체 기판(1)상에 플라즈마화학기상증착(Plasma Enhanced Chemical Vapor Deposition: 이하 PECVD라 한다.)으로 제 1 절연층(5)을 형성한다.First, as shown in FIG. 1A, a bottom layer 2 is formed on a semiconductor substrate 1, a first conductive layer pattern 4 is formed on the base layer 2, and the first layer is formed. A first insulating layer 5 is formed on the semiconductor substrate 1 including the first conductive layer pattern 4 by plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD).

다음, 도 1b에 도시된 바와 같이, 상기 제 1 절연층(5)상에 평탄화를 목적으로 유동성이 낮은 무기SOG를 도포하고, 이를 열처리하여 무기SOG층(6)을 형성한다.Next, as shown in FIG. 1B, an inorganic SOG having low fluidity is coated on the first insulating layer 5 for the purpose of planarization, and the inorganic SOG layer 6 is formed by heat treatment.

다음, 도 1c에 도시된 바와 같이, 상기 무기SOG층(6)상에 제 2 절연층(7)을 PECVD에 의해 형성하고, 상기 제 2 절연층(7)상에 감광층패턴(도시되지않음)을 형성한다.Next, as shown in FIG. 1C, a second insulating layer 7 is formed on the inorganic SOG layer 6 by PECVD, and a photosensitive layer pattern (not shown) is formed on the second insulating layer 7. ).

다음, 도 1d에 도시된 바와 같이, 상기 감광층패턴을 마스크로 하여 상기 제 1 도전층패턴(4)상의 일정영역이 노출되도록 상기 제 2 절연층(7), 무기SOG층(6) 및 제 1 절연층(5)을 차례로 에칭하여 비아(8)를 형성한다.Next, as shown in FIG. 1D, the second insulating layer 7, the inorganic SOG layer 6, and the second insulating layer 7 are exposed so that a predetermined region on the first conductive layer pattern 4 is exposed using the photosensitive layer pattern as a mask. 1 Insulating layer 5 is sequentially etched to form vias 8.

다음, 도 1e에 도시된 바와 같이, 상기 비아(8) 및 제 2 절연층(7)상에 제 2 도전층패턴(9)을 형성함으로서 무기SOG층(6)을 이용한 종래 메탈층간의 평탄화공정이 완료된다.Next, as shown in FIG. 1E, a planarization process between the conventional metal layers using the inorganic SOG layer 6 is formed by forming a second conductive layer pattern 9 on the via 8 and the second insulating layer 7. Is complete.

상기와 같은 무기SOG를 이용한 종래 메탈층간의 평탄화공정에 있어서, 유기SOG을 이용한 평탄화공정과 비해 SOG층을 반드시 에칭할 필요가 없고, 비아형성을 위한 에칭공정에 있어서 미량첨가되는 산소와, 에칭후에 감광층패턴 및 비아영역내에 존재하는 잔류물질의 제거시에 수반되는 산소플라즈마에 대해 탄소성분이 함유되지 않은 무기SOG는 반응하지 않아서 손상을 입지 않는 반면에, 탄소성분의 비함유로 인해 열처리공정시 무기SOG를 구성하는 원자들의 재배열이 없고, 유동성이 적어 평탄도특성이 저하되는 문제점이 있었다.In the conventional planarization process between the metal layers using the inorganic SOG as described above, the SOG layer does not necessarily need to be etched as compared with the planarization process using the organic SOG. Inorganic SOG, which does not contain carbon, does not react with the oxygen plasma that is involved in removing residual materials in the photosensitive layer pattern and via region, and does not react. There is no problem in that the rearrangement of atoms constituting the inorganic SOG, and the fluidity is low, the flatness characteristics are reduced.

이어서, 유기SOG를 이용한 종래 메탈층간의 평탄화공정에 대해 첨부된 도면, 도 2a∼2f을 참조하여 설명하기로 한다.Next, a planarization process between metal layers using organic SOG will be described with reference to the accompanying drawings and FIGS. 2A to 2F.

먼저, 도 2a에 도시된 바와 같이, 반도체 기판(1)상에 기저층(bottom layer)(2)을 형성하고, 상기 기저층(2)상에 제 1 도전층패턴(4)을 형성하고, 상기 제 1 도전층패턴(4)을 포함한 상기 반도체 기판(1)상에 제 1 절연층(5)을 PECVD에 의해 형성한다.First, as shown in FIG. 2A, a bottom layer 2 is formed on a semiconductor substrate 1, a first conductive layer pattern 4 is formed on the base layer 2, and the first layer is formed. A first insulating layer 5 is formed on the semiconductor substrate 1 including the first conductive layer pattern 4 by PECVD.

다음, 도 2b에 도시된 바와 같이, 상기 제 1 절연층(5)상에 평탄화를 목적으로 유동성의(flowable)이 높은 유기SOG를 도포하고, 이를 열처리하여 유기SOG층(3)을 형성한다. 이때, 상기 유기SOG층(3)은 더욱 평탄화된다.Next, as shown in FIG. 2B, a highly flowable organic SOG is coated on the first insulating layer 5 for the purpose of planarization, and the organic SOG layer 3 is formed by heat treatment. At this time, the organic SOG layer 3 is further planarized.

다음, 도 2c에 도시된 바와 같이, 상기 제 1 도전층패턴(4)상에 형성된 상기 제 1 절연층(5)의 상면이 노출될 때 까지 상기 유기SOG층(3)을 에치백(etchback)한다.Next, as shown in FIG. 2C, the organic SOG layer 3 is etched back until the top surface of the first insulating layer 5 formed on the first conductive layer pattern 4 is exposed. do.

다음, 도 2d에 도시된 바와 같이, 상기 노출된 제 1 절연층(5) 및 에칭된 유기SOG층(3)의 상면에 제 2 절연층(7)을 PECVD에 의해 형성한다.Next, as shown in FIG. 2D, a second insulating layer 7 is formed by PECVD on top of the exposed first insulating layer 5 and the etched organic SOG layer 3.

다음, 도 2e에 도시된 바와 같이, 상기 제 2 절연층(7)상에 감광층패턴(도시되지않음)을 형성한 후, 이를 마스크로 하여 상기 제 1 도전층패턴(4)상의 일정영역이 노출되도록 상기 제 2 절연층(7)을 에칭하여 비아(8)를 형성한다.Next, as shown in FIG. 2E, after forming a photosensitive layer pattern (not shown) on the second insulating layer 7, a predetermined region on the first conductive layer pattern 4 is formed as a mask. The second insulating layer 7 is etched to expose the vias 8.

다음, 도 2f에 도시된 바와 같이, 상기 비아(8) 및 제 2 절연층(7)상에 제 2 도전층패턴(9)을 형성함으로서 유기SOG(3)를 이용한 종래 메탈층간의 평탄화공정이 완료된다.Next, as shown in FIG. 2F, a planarization process between the conventional metal layers using the organic SOG 3 is performed by forming a second conductive layer pattern 9 on the via 8 and the second insulating layer 7. Is done.

상기와 같은 유기SOG를 이용한 종래 메탈층간의 평탄화공정에 있어서, 반드시 유기SOG층을 에칭해야 한다. 만일 유기SOG층을 에칭하지 않으면, 비아형성을 위한 에칭공정시에 미량첨가되는 산소와, 에칭후에 감광층패턴 및 비아영역내에 존재하는 잔류물질의 제거시에 수반되는 산소플라즈마에 의해 유기SOG의 탄소성분이 산소와 반응하여 유기SOG층이 손상(damage)되는 문제점이 있었다.In the conventional planarization process between the metal layers using the organic SOG as described above, the organic SOG layer must be etched. If the organic SOG layer is not etched, the carbon of the organic SOG may be reduced by oxygen added in the etching process for forming vias and oxygen plasma accompanying the removal of residual material present in the photosensitive layer pattern and via region after etching. There is a problem that the organic SOG layer is damaged by the component reacts with oxygen.

또한, 디램(DRAM)의 제조에 있어서, 셀영역과 주변영역의 초기표고차에 의해 비아가 형성되는 영역내의 유기SOG를 에치백공정으로 제거시, 절연층/유기SOG층의 에칭선택비(etching selectivity)조절이 어렵고, 이로 인해 에칭량이 증가 되어 도전층이 손상을 입을 수 있고, 이로 인해 공정마진(process margain)이 좁아지고, 또한 로딩효과(loading effect)에 기인한 평탄도특성이 나빠지는 문제점이 있었다.Also, in the manufacture of DRAM, etching selectivity of the insulating layer / organic SOG layer is removed when the organic SOG in the region where the via is formed due to the initial elevation difference between the cell region and the peripheral region is removed by an etch back process. It is difficult to control, which may increase the etching amount and damage the conductive layer, resulting in a narrow process margain and a deterioration in flatness characteristics due to the loading effect. there was.

따라서, 본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 메탈층간에 형성된 유기물질층을 화학적공정(chemical process)에 의해 무기물질층으로 변화시킴으로서 애치백공정이 필요없는 반도체 제조공정에서의 무기층 형성방법을 제공한다.Accordingly, an object of the present invention is to change the organic material layer formed between the metal layers to an inorganic material layer by a chemical process in order to solve the above problems, the inorganic layer in the semiconductor manufacturing process that does not require an ashback process It provides a formation method.

본 발명의 다른 목적은 비아형성시 미량첨가되는 산소와, 에칭후 비아영역내에 존재하는 잔류물질제거시에 수반되는 산소플라즈마에 대해 손상이 없는 반도체 제조공정에서의 무기층 형성방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming an inorganic layer in a semiconductor manufacturing process which is free of damage to oxygen added in the formation of vias and oxygen plasma accompanying removal of residual substances present in the via region after etching.

본 발명은 또 다른 목적은 평탄도특성이 우수한 반도체 제조공정에서의 무기층 형성방법을 제공함에 있다.Another object of the present invention is to provide a method for forming an inorganic layer in a semiconductor manufacturing process having excellent flatness characteristics.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 바람직한 일실시예에 따르면, 반도체 기판상에 제 1 도전층패턴을 형성하는 공정과, 상기 제 1 도전층패턴을 포함한 반도체 기판상에 SOG(SOG)층을 형성하는 공정과, 상기 SOG층을 오존 분위기에서 열처리하는 공정과, 상기 SOG층상에 제 1 절연층을 형성하는 공정과, 상기 제 1 도전층패턴이 노출되도록 에칭하여 비아를 형성하는 공정과, 상기 비아를 포함한 제 1 절연층상에 제 2 도전층패턴을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체 제조공정에서의 무기층 형성방법을 제공한다.According to a preferred embodiment of the present invention for achieving the above object, a step of forming a first conductive layer pattern on a semiconductor substrate, and SOG (SOG) on a semiconductor substrate including the first conductive layer pattern Forming a layer, heat-treating the SOG layer in an ozone atmosphere, forming a first insulating layer on the SOG layer, etching to expose the first conductive layer pattern, and forming a via; And a step of forming a second conductive layer pattern on the first insulating layer including the via.

상기 오존분위기에서의 열처리는 챔버 또는 퍼니스에서 수행되고, 그들의 압력조건은 1∼10torr이고, 오존/산소의 농도조건은 2∼12wt%이고, 오존가스흐름조건은 1000∼5000sccm인 것을 특징으로 한다.The heat treatment in the ozone atmosphere is carried out in a chamber or a furnace, their pressure conditions are 1 to 10 torr, the ozone / oxygen concentration condition is 2 to 12 wt%, and the ozone gas flow condition is 1000 to 5000 sccm.

도 1a∼1f는 무기SOG를 이용한 종래 메탈층간 평탄화공정을 도시한 단면도.1A to 1F are cross-sectional views showing a conventional interlayer planarization process using inorganic SOG.

도 2a∼2f는 유기SOG를 이용한 종래 메탈층간 평탄화공정을 도시한 단면도.2A to 2F are cross-sectional views showing a conventional interlayer planarization process using organic SOG.

도 3a∼3f는 본 발명에 의한 무기화된 SOG를 이용한 메탈층간 평탄화공정을 도시한 단면도.3A to 3F are cross-sectional views showing an intermetallic planarization process using inorganic SOG according to the present invention.

** 도면의 주요부분에 대한 부호설명 **** Explanation of symbols on main parts of the drawing **

11 : 반도체 기판 12 : 기저층(bottom layer)11 semiconductor substrate 12 bottom layer

14 : 제 1 도전층패턴 15 : 제 1 절연층14: first conductive layer pattern 15: first insulating layer

16 : 유기SOG층 17 : 무기SOG층16: organic SOG layer 17: inorganic SOG layer

18 : 제 2 절연층 19 : 비아(via)18: second insulating layer 19: via

20 : 제 2 도전층패턴20: second conductive layer pattern

이하, 본 발명에 의한 반도체 제조공정에서의 무기층 형성방법을 설명한다.Hereinafter, the inorganic layer forming method in the semiconductor manufacturing process according to the present invention will be described.

도 3a∼3f는 본 발명에 의한 메탈층간의 평탄화공정을 순차적으로 도시한 단면도로서, 도시된 바와 같이, 도 3a에 도시된 바와 같이, 반도체 기판(11)상에 기저층(bottom layer)(12)을 형성하고, 상기 기저층(12)상에 제 1 도전층패턴(14)을 형성하고, 상기 제 1 도전층패턴(14)을 포함한 상기 기저층(12)상에 플라즈마화학기상증착(Plasma Enhanced Chemical Vapor Deposition: 이하 PECVD라 한다.)으로 제 1 절연층(15)을 형성한다.3A to 3F are cross-sectional views sequentially illustrating the planarization process between the metal layers according to the present invention. As shown in FIG. 3A, as shown in FIG. 3A, a bottom layer 12 is formed on the semiconductor substrate 11. Forming a first conductive layer pattern 14 on the base layer 12, and plasma-enhanced chemical vapor deposition on the base layer 12 including the first conductive layer pattern 14. Deposition: hereinafter referred to as PECVD) to form the first insulating layer 15.

다음, 도 3b에 도시된 바와 같이, 상기 제 1 절연층(15)상에 유기SOG층(16)을 형성한다. 상기 유기SOG층(16)은 다량의 CH3가 함유되어 있고, 이에 의하여 열처리에 의한 리플로우(reflow)특성이 우수하여 평탄화물질로 널리 사용된다.Next, as shown in FIG. 3B, an organic SOG layer 16 is formed on the first insulating layer 15. The organic SOG layer 16 contains a large amount of CH 3 , thereby having excellent reflow characteristics by heat treatment, and thus is widely used as a planarization material.

다음, 도 3c에 도시된 바와 같이, 상기 유기SOG층(16)을 포함한 상기 반도체 기판(11)을 챔버 또는 퍼니스(도시되지않음)에 넣은 후, 오존 분위기에서 열처리하여 상기 유기SOG층(

Figure kpo00001
구조)(16)을 화학적공정에 의해 무기SOG층(
Figure kpo00002
)(17)으로 변화시킨다. 이때, 상기 챔버 또는 퍼니스의 압력조건은 1∼10torr이고, 오존(O3) 대 산소(O2)의 농도조건은 2∼12wt%이고, 오존의 가스흐름조건은 1000∼5000sccm이다. 그리고, 상기 가스흐름도의 단위 sccm은 Standard Cubic Cm/Min의 약어이고, 상기한 조건하에서의 반응식 1은 다음과 같다.Next, as shown in FIG. 3C, the semiconductor substrate 11 including the organic SOG layer 16 is placed in a chamber or a furnace (not shown), and then heat-treated in an ozone atmosphere to form the organic SOG layer (
Figure kpo00001
Structure) by means of a chemical process
Figure kpo00002
(17). At this time, the pressure condition of the chamber or the furnace is 1 to 10 torr, the concentration condition of ozone (O 3 ) to oxygen (O 2 ) is 2 to 12wt%, the gas flow conditions of ozone is 1000 to 5000sccm. In addition, the unit sccm of the gas flow rate is an abbreviation of Standard Cubic Cm / Min, and Scheme 1 under the above conditions is as follows.

Figure kpo00003
Figure kpo00003

다음, 도 3d에 도시된 바와 같이, 상기 무기SOG층(17)상에 제 2 절연층(18)을 형성한다. 상기 제 2 절연층(18)은 PECVD에 의해 증착된다.Next, as shown in FIG. 3D, a second insulating layer 18 is formed on the inorganic SOG layer 17. The second insulating layer 18 is deposited by PECVD.

다음, 도 3e에 도시된 바와 같이, 상기 제 2 절연층(18)상에 감광층 패턴(도시되지 않음)을 형성하고, 이를 마스크로 하여 상기 제 1 도전층패턴(14)상의 일정영역이 노출되도록 상기 제 2 절연층(18) 및 무기SOG층(17)을 에칭하여 비아(19)를 형성한다. 이때, 비아(19)형성시에 미량첨가되는 산소와, 에칭후 비아(19)영역내에 존재하는 잔류물질 및 감광층제거시에 수반되는 산소 플라즈마에 의해 무기화된 SOG층은 손상받지 않는다.Next, as shown in FIG. 3E, a photosensitive layer pattern (not shown) is formed on the second insulating layer 18, and a predetermined region on the first conductive layer pattern 14 is exposed using the mask. The second insulating layer 18 and the inorganic SOG layer 17 are etched to form the vias 19 so as to form the vias 19. At this time, the SOG layer inorganicized by the oxygen added in the trace 19 when the via 19 is formed, the residual material present in the via 19 region after etching, and the oxygen plasma accompanying the removal of the photosensitive layer are not damaged.

다음, 도 3f에 도시된 바와 같이, 상기 비아(19)를 포함한 상기 제 2 절연층(18)상에 제 2 도전층패턴(20)을 형성함으로서 본 발명에 의한 반도체 제조공정에서의 무기층형성공정이 완료된다.Next, as shown in FIG. 3F, an inorganic layer is formed in the semiconductor manufacturing process according to the present invention by forming a second conductive layer pattern 20 on the second insulating layer 18 including the vias 19. The process is complete.

상기한 바와 같은 본 발명에 의한 반도체 제조공정에서의 무기층형성방법은 에치백공정을 수행하지 않으므로 에치백시 문제시된 절연층/SOG층의 에칭선택비의 조절 및 공정상의 마진문제가 해결되고, 무기SOG로의 변화이전의 유기SOG의 초기평탄화상태를 그대로 유지할 수 있고, 변화된 무기SOG로 인해 비아형성시 산소 플라즈마에 대한 저항력이 높아지는 효과가 있다.Since the inorganic layer forming method in the semiconductor manufacturing process according to the present invention as described above does not perform the etch back process, the problem of controlling the etching selectivity of the insulating layer / SOG layer during etch back problem and the process margin problem are solved. It is possible to maintain the initial leveling state of organic SOG before the change to inorganic SOG, and the changed inorganic SOG has an effect of increasing resistance to oxygen plasma during via formation.

Claims (4)

반도체 기판(11)상에 제 1 도전층패턴(14)을 형성하는 공정과;Forming a first conductive layer pattern 14 on the semiconductor substrate 11; 상기 제 1 도전층패턴(14)을 포함한 반도체 기판(11)상에 SOG층(16)을 형성하는 공정과;Forming a SOG layer (16) on the semiconductor substrate (11) including the first conductive layer pattern (14); 상기 SOG층(16)을 오존(O3)분위기에서 열처리하는 공정과;Heat-treating the SOG layer 16 in an ozone (O 3 ) atmosphere; 상기 SOG층(17)상에 제 1 절연층(18)을 형성하는 공정과;Forming a first insulating layer (18) on said SOG layer (17); 상기 제 1 도전층패턴(14)이 노출되도록 에칭하여 비아(via)(19)를 형성하는 공정과;Etching to expose the first conductive layer pattern (14) to form a via (19); 상기 비아(19)를 포함한 제 1 절연층(18)상에 제 2 도전층패턴(20)을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체 제조공정에서의 무기층 형성방법.Forming a second conductive layer pattern (20) on the first insulating layer (18) including the via (19). 제 1 항에 있어서, 상기 제 1 도전층패턴(14)상에 형성하는 SOG층은 유기SOG층(16)인 것을 특징으로 하는 반도체 제조공정에서의 무기층 형성방법.The method according to claim 1, wherein the SOG layer formed on the first conductive layer pattern (14) is an organic SOG layer (16). 제 1 항에 있어서, 상기 오존분위기에서의 열처리공정은 챔버 또는 퍼니스의 압력조건은 1∼10torr이고, 오존/산소의 농도조건은 2∼12wt%이고, 오존의 가스흐름조건은 1000∼5000sccm인 것을 특징으로 하는 반도체 제조공정에서의 무기층 형성방법.According to claim 1, wherein the heat treatment step in the ozone atmosphere is the pressure condition of the chamber or the furnace is 1 to 10torr, the ozone / oxygen concentration condition is 2 to 12wt%, the gas flow condition of the ozone is 1000 to 5000sccm An inorganic layer forming method in a semiconductor manufacturing process characterized by the above-mentioned. 제 1 항에 있어서, 상기 오존분위기에서 열처리와 상기 절연층(18)의 증착은 동일챔버내에서 연속수행하는 것을 특징으로 하는 반도체 제조공정에서의 무기층 형성방법.The method of claim 1, wherein the heat treatment and the deposition of the insulating layer (18) in the ozone atmosphere are carried out continuously in the same chamber.
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