KR100298180B1 - Method for forming contact hole in semiconductor - Google Patents
Method for forming contact hole in semiconductor Download PDFInfo
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- KR100298180B1 KR100298180B1 KR1019980025219A KR19980025219A KR100298180B1 KR 100298180 B1 KR100298180 B1 KR 100298180B1 KR 1019980025219 A KR1019980025219 A KR 1019980025219A KR 19980025219 A KR19980025219 A KR 19980025219A KR 100298180 B1 KR100298180 B1 KR 100298180B1
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- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229920000642 polymer Polymers 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 29
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 17
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- NJCQVAKYBOCUCS-UHFFFAOYSA-N [C].F Chemical class [C].F NJCQVAKYBOCUCS-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
선택적 폴리머 증착을 이용하여 2단 기울기를 갖는 콘택홀을 형성함으로써 하부구조와의 오정렬을 피할 수 있는 마진을 확보하고 콘택홀의 접촉저항을 개선하는데 적합한 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 이를 위하여 본 발명은 소정 공정이 완료된 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막상에 감광막을 도포하고 선택적으로 패터닝하여 감광막패턴을 형성하는 단계; 카본 비율이 상대적으로 높은 플라즈마를 이용하여 상기 절연막을 일부 식각하여 상기 감광막패턴의 측벽 및 일부 식각된 절연막의 측벽에 폴리머를 증착하는 단계; 및 상기 폴리머를 식각마스크로 하고 카본 비율이 상대적으로 낮은 가스를 이용하여 상기 절연막이 수직프로파일을 갖도록 식각하여 2단 기울기를 갖는 콘택홀을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method for forming a contact hole of a semiconductor device suitable for securing a margin to avoid misalignment with an underlying structure and improving contact resistance of a contact hole by forming a contact hole having a two-step slope using selective polymer deposition. The present invention comprises the steps of forming an insulating film on a semiconductor substrate having a predetermined process; Forming a photoresist pattern by coating and selectively patterning a photoresist on the insulating layer; Partially etching the insulating layer using a plasma having a relatively high carbon ratio to deposit a polymer on the sidewall of the photoresist pattern and the sidewall of the partially etched insulating layer; And etching the insulating film to have a vertical profile by using the polymer as an etching mask and using a gas having a relatively low carbon ratio to form a contact hole having a two-stage slope.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 선택적 폴리머 증착을 통한 반도체소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device through selective polymer deposition.
최근에 반도체소자가 고집적화되어감에 따라 콘택홀을 형성하는데 공정마진이 부족하여 하부구조에 실리콘패드등을 미리 형성하여 나중에 실리콘패드에 콘택홀이 연결되도록 하는 것과 같은 방법이 개발되어 사용되어 오고 있다. 이러한 기술을 적용할때에는 동일한 크기의 콘택홀을 형성할때 그 깊이가 서로 다른 콘택홀을 동시에 형성해야 하는 어려움이 있다. 종래기술에 의한 콘택홀을 형성방법을 크게 2가지로 구분하여 설명하면 다음과 같다.Recently, as semiconductor devices have been highly integrated, a process margin for forming contact holes has been lacked. Thus, a method such as forming a silicon pad in the lower structure in advance so that the contact hole is connected to the silicon pad has been developed and used. . When applying this technique, there is a difficulty in forming contact holes having different depths at the same time when forming contact holes of the same size. When forming a contact hole according to the prior art divided into two largely described as follows.
먼저, 도 1에 나타낸 바와 같이 콘택홀이 일정한 기울기를 갖도록 조절하는 테이퍼 식각에 의한 콘택홀 형성방법이 그 하나이다. 도시된 바와 같이 콘택홀 입구의 크기를 일정하지만 그 깊이가 서로 다른 지역에 최종 콘택홀이 형성되는 관계로 하부구조와 연결되는 지역에서는 그 크기에 깊이에 반비례하여 작아진다. 그 결과, 콘택홀이 깊은 지역에 형성될때는 하부구조와의 연결면적이 매우 작아지므로 접촉저항이 증가하는 문제가 있다. 그 깊이가 더 깊을 때에는 콘택홀이 연결되지 않을 가능성도 있다. 그러나 반대로 하부구조에 미리 형성된 실리콘패드(4)와 연결할때는 패드의 크기를 공정한계상 콘택홀 크기보다 어느 이상 크게 할 수 없기 때문에 최종 콘택홀의 크기가 작을수록 오정렬을 피할 수 있는 공정마진이 증가하는 장점이 있다.First, as shown in FIG. 1, a method of forming a contact hole by taper etching for adjusting the contact hole to have a constant slope is one of them. As shown in the figure, the contact hole inlet is constant but the depth is inversely proportional to the depth in the region connected with the substructure because the final contact hole is formed in the regions having different depths. As a result, when the contact hole is formed in a deep area, the connection area with the substructure becomes very small, which causes a problem of increasing contact resistance. If the depth is deeper, the contact hole may not be connected. On the contrary, when the silicon pad 4 is formed in the substructure, the pad size cannot be larger than the contact hole size due to the process limit. Therefore, the smaller the final contact hole is, the more the process margin can be avoided. There is this.
도 2는 콘택홀이 90。에 가까운 수직의 기울기를 갖도록 조절하는 방법으로서, 이 경우에는 도 1의 경우와는 반대로 콘택홀의 깊이에 관계없이 최종 콘택홀이 일정한 크기를 갖기 때문에 접촉저항이나 콘택홀이 오픈되지 않는 현상을 피할 수 있는 장점이 있다. 그러나 반대로 이 경우에는 오정렬이 발생했을때 하부구조의 실리콘패드등과 벗어나게 되면 도면에서 보듯이 콘택홀이 실리콘패드(4)와 전극(2)에 동시에 형성되어 단락(S)을 유발할 가능성이 높다.2 is a method of adjusting the contact hole to have a vertical inclination close to 90 DEG. In this case, the contact hole or the contact hole has a constant size regardless of the depth of the contact hole as opposed to the case of FIG. This has the advantage of avoiding the phenomenon of not opening. On the contrary, in this case, when misalignment occurs, the contact hole is formed in the silicon pad 4 and the electrode 2 at the same time, as shown in the drawing.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 선택적 폴리머 증착을 이용하여 2단 기울기를 갖는 콘택홀을 형성함으로써 하부구조와의 오정렬을 피할 수 있는 마진을 확보하고 콘택홀의 접촉저항을 개선할 수 있는 방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above problems, by forming a contact hole having a two-stage slope using selective polymer deposition to ensure a margin that can avoid misalignment with the underlying structure and improve the contact resistance of the contact hole Its purpose is to provide a method.
도 1 및 도 2는 종래기술에 의한 콘택홀 형성시의 문제점을 도시한 도면,1 and 2 is a view showing a problem when forming a contact hole according to the prior art,
도 3a 내지 도 3c는 본 발명에 의한 선택적 폴리머증착을 통한 반도체소자의 콘택홀 형성방법을 도시한 공정순서도.3A to 3C are process flowcharts illustrating a method for forming a contact hole in a semiconductor device through selective polymer deposition according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
2 : 게이트전극 4 : 도전성패드2 gate electrode 4 conductive pad
10 : 절연막 11 : 감광막패턴10 insulating film 11: photosensitive film pattern
12 : 폴리머12: polymer
상기 목적을 달성하기 위한 본 발명의 반도체소자의 콘택홀 형성방법은 소정 공정이 완료된 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막상에 감광막을 도포하고 선택적으로 패터닝하여 감광막패턴을 형성하는 단계; 카본 비율이 상대적으로 높은 플라즈마를 이용하여 상기 절연막을 일부 식각하여 상기 감광막패턴의 측벽 및 일부 식각된 절연막의 측벽에 폴리머를 증착하는 단계; 및 상기 폴리머를 식각마스크로 하고 카본 비율이 상대적으로 낮은 가스를 이용하여 상기 절연막이 수직프로파일을 갖도록 식각하여 2단 기울기를 갖는 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.Contact hole forming method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film on a semiconductor substrate is completed a predetermined process; Forming a photoresist pattern by coating and selectively patterning a photoresist on the insulating layer; Partially etching the insulating layer using a plasma having a relatively high carbon ratio to deposit a polymer on the sidewall of the photoresist pattern and the sidewall of the partially etched insulating layer; And etching the insulating film to have a vertical profile by using the polymer as an etching mask and using a gas having a relatively low carbon ratio to form a contact hole having a two-stage slope.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3a 내지 도 3c에 본 발명에 의한 선택적 폴리머 증착을 통한 반도체소자의 콘택홀 형성방법을 공정순서에 따라 나타내었다.3A to 3C illustrate a method of forming a contact hole in a semiconductor device through selective polymer deposition according to the present invention according to a process sequence.
도 3a를 참조하면, 하부구조로서 게이트전극(2) 및 도전성패드(4)등이 형성되어 있는 반도체기판(도시하지 않음)상에 절연막(10)을 형성한 후, 그 상부에 감광막을 을 도포하고 노광 및 현상을 통해 콘택홀 형성용 감광막패턴(11)으로 패터닝한다. 여기서, 상기 게이트전극(2)은 전도성물질을 포함하여 적층된 구조로 형성될 수 있으며, 상기 게이트전극(2)의 측면에는 측벽스페이서가 형성될 수 있다. 그리고 상기 도전성패드(4)는 후속 콘택홀을 통해 금속배선이 반도체기판에 전기적으로 연결되도록 한다. 또한 상기 절연막(10)은 SiO2나 SiON성분이 포함된 물질로 형성하며, 상기 감광막패턴(11)은 하부층의 종류 및 폴리머 증착타겟에 따라서 용해억제형 i-라인 포토레지스트나 화학증폭형 DUV(Deep UltraViolet) 포토레지스트로 형성한다.Referring to FIG. 3A, an insulating film 10 is formed on a semiconductor substrate (not shown) on which a gate electrode 2, a conductive pad 4, and the like are formed as a lower structure, and then a photosensitive film is coated thereon. Then, the pattern is formed into the photoresist pattern 11 for forming a contact hole through exposure and development. The gate electrode 2 may be formed of a stacked structure including a conductive material, and sidewall spacers may be formed on side surfaces of the gate electrode 2. The conductive pad 4 also allows the metallization to be electrically connected to the semiconductor substrate through subsequent contact holes. In addition, the insulating film 10 is formed of a material containing SiO 2 or SiON component, the photosensitive film pattern 11 is a melt-inhibited i-line photoresist or chemically amplified DUV (depending on the type of the lower layer and the polymer deposition target) Deep UltraViolet) photoresist.
이어서 도 3b를 참조하면, 상기 감광막패턴(11)이 존재하는 상황에서 이후 원하는 크기로 패턴을 형성하기 위하여 감광막에 존재하는 카본(carbon)성분과 반응하여 쉽게 폴리머를 발생시키는 가스, 예를 들면, HBr, N2, O2또는 CHF3, C2F6, C3F8등 카본 플로라이드(carbon floride)나 카본 하이드로플로라이드(carbon hydro-floride)계열의 가스만을 사용하여 플라즈마를 발생시킨다. 이러한 가스들을 단독으로 또는 2-3가지 혼합하여 플라즈마를 발생시킬 수 있다. 여기서, 카본 플로라이드나 카본 하이드로플로라이드 계열의 가스를 사용할 때에는 가급적 카본의 비율이 높은 C3H8, C4F10등을 이용하는 것이 폴리머 생성에 유리하다. 이렇게 발생시킨 플라즈마에서 전하를 띠는 이온들이 기판에 입사되어 스캐터링(scattering)을 일으키는데, 이때 플라즈마에서 입사된 이온들과 하부층의 식각물질인 Si, SiO2, SiON등의 Si, O, N성분과 감광막의 카본이 서로 반응하여 비휘발성 폴리머(12)를 생성시킨다. 여기서, 비휘발성 폴리머(12)는 감광막 패턴(11)의 측면에 증착되어 콘택홀의 크기를 감소시키는데, 상기 비휘발성 폴리머(12)는 감광막 표면뿐 아니라 식각해야할 표면(즉, 노출된 절연막(10)의 표면)에도 증착되기 쉬운데 이는 후속공정인 식각공정을 어렵게 한다. 그러므로 폴리머(12)를 증착할 때 감광막패턴(11)의 측벽에만 선택적으로 증착되게 조절하는 것이 매우 중요한데, 폴리머(12)를 선택적으로 증착되도록 하기 위해서는 폴리머 증착을 위한 플라즈마 형성시 웨이퍼가 놓이는 전극에 바이어스를 가하여 입사되는 이온의 직진성을 강화시켜 줌으로써 (즉, 이온 에너지를 증가시킴으로써) 감광막 패턴(11)이 존재하지 않는 지역(식각할 지역)에 강한 에너지를 갖는 이온이 부딪혀 표면에는 폴리머가 증착되지 않도록 하고 감광막패턴(11)의 측면에만 증착되도록 해야 한다. 구체적으로 설명하면 표면에 폴리머가 증착되지 않는 것이 아니라 증착과 동시에 입사되는 이온에 의하여 증착된 폴리머가 분해되는 것이다. 도 3b에 도시된 바와 같이 폴리머를 증착하는 과정에서 하부구조의 Si, O, N성분등과 반응하기 때문에 하부구조가 일부는 식각된다. 이때, 식각과 동시에 감광막패턴(11)의 측벽에 폴리머(12)가 증착되므로 콘택홀의 윗부분은 일정한 기울기(A)를 가지게 된다. 플라즈마 발생 시간을 조절함으로써 상기 기울기의 위치를 조절할 수 있다.Subsequently, referring to FIG. 3B, a gas that easily generates a polymer by reacting with a carbon component present in the photosensitive film in order to form a pattern having a desired size in a situation where the photosensitive film pattern 11 is present, for example, HBr, N 2 , O 2 or CHF 3 , C 2 F 6 , C 3 F 8, such as carbon floride (carbon floride) or carbon hydro-fluoride (carbon hydro- floride) -based gas is used to generate the plasma. These gases may be mixed alone or in combination of 2-3 to generate a plasma. Here, when using carbon fluoride or carbon hydrofluoride-based gas, it is advantageous to use a polymer such as C 3 H 8 , C 4 F 10 and the like, where the ratio of carbon is high. The charged ions in the plasma are incident on the substrate to cause scattering. In this case, Si, O, and N components such as Si, SiO 2 , SiON, etc. And carbon in the photosensitive film react with each other to produce the nonvolatile polymer 12. Here, the nonvolatile polymer 12 is deposited on the side of the photoresist pattern 11 to reduce the size of the contact hole. The nonvolatile polymer 12 is not only a surface of the photoresist, but also a surface to be etched (that is, the exposed insulating film 10). Surface), which makes the subsequent etching process difficult. Therefore, when depositing the polymer 12, it is very important to control the selective deposition only on the sidewall of the photoresist pattern 11. In order to selectively deposit the polymer 12, the electrode is placed on the electrode on which the wafer is placed during plasma formation for the polymer deposition. By applying a bias to enhance the linearity of the incident ions (i.e., increasing the ion energy), ions having strong energy are hit in areas where the photoresist pattern 11 is not present (area to be etched), and polymers are not deposited on the surface. And to be deposited only on the side of the photoresist pattern (11). Specifically, the polymer is not deposited on the surface, but the deposited polymer is decomposed by ions incident at the same time as the deposition. As shown in FIG. 3B, some of the substructures are etched because they react with Si, O, and N components of the substructures during the deposition of the polymer. At this time, since the polymer 12 is deposited on the sidewall of the photoresist pattern 11 at the same time as the etching, the upper portion of the contact hole has a constant slope (A). The position of the inclination may be adjusted by adjusting the plasma generation time.
상기 폴리머 증착공정을 더욱 상세히 설명하면, 우선, 폴리머를 증착하기 위한 플라즈마장비로는 Helicon(PMT-electrotech사), HDP(High Density Plasma), TCP(Transformer Coupled Plasma), ICP(Inductively Coupled Plasma), ECR (Electron Cyclotron Resonance)등의 고밀도 플라즈마 소오스를 사용하는 장비를 이용하며, 병렬 플레이트(Parallel plate), RIE(Reactive Ion Etching), MERIE(Magnetically Enhanced RIE)등의 장비를 사용할 수도 있다. 상기 플라즈마 형성시 압력은 1-1000mTorr, 가스의 양은 1-200sccm, 소오스파워 및 바이어스파워는 각각 10-3000W, 전극의 온도는 -50℃∼300℃로 조절하는 것이 바람직하다.The polymer deposition process will be described in more detail. First, plasma equipment for depositing polymers may include Helicon (PMT-electrotech), HDP (High Density Plasma), TCP (Transformer Coupled Plasma), ICP (Inductively Coupled Plasma), Equipment using high density plasma sources such as ECR (Electron Cyclotron Resonance) can be used, and equipment such as parallel plate, reactive ion etching (RIE), and magnetically enhanced RIE (MERIE) can also be used. When the plasma is formed, the pressure is 1-1000 mTorr, the amount of gas is 1-200 sccm, the source power and the bias power are respectively 10-3000 W, and the temperature of the electrode is preferably adjusted to -50 ° C to 300 ° C.
도 3c를 참조하면, 상기 감광막패턴(11)과 그 측면에 증착된 폴리머(12)를 함께 식각장벽으로 사용하여 절연막(10)을 식각하여 수직형태의 콘택홀을 형성한 후, 감광막패턴(11)과 폴리머(12)를 제거한다. 도시된 바와 같이 콘택홀의 기울기를 수직에 가깝도록 조절하면 2단 기울기를 갖도록 할 수 있다. 수직 형태를 갖도록 식각할때는 CF4, CHF3등의 카본 비율이 낮은 가스를 Ar이나 Co 또는 O2등과 혼합하여 사용해야 식각과정에서 부산물로 발생되는 폴리머들이 콘택홀 내부에 쌓이지 않고 밖으로 배출되어 콘택홀이 형성될 수 있다. Ar이나 Co 또는 O2는 카본 플로라이드나 카본 하이드로플로라이드 계열 가스에 약 10-300% 범위내에서 첨가하여 사용한다.Referring to FIG. 3C, the insulating layer 10 is etched using the photoresist pattern 11 and the polymer 12 deposited on the side thereof as an etch barrier to form a vertical contact hole, and then the photoresist pattern 11 ) And the polymer (12). As shown in the drawing, by adjusting the inclination of the contact hole to be close to the vertical, it is possible to have a two-stage inclination. When etching to have a vertical shape, a gas with low carbon ratio such as CF 4 or CHF 3 must be mixed with Ar, Co or O 2, etc., and polymers generated as by-products during the etching process are discharged out of the contact hole without being accumulated inside the contact hole. Can be formed. Ar, Co, or O 2 is added to the carbon fluoride or carbon hydrofluoride gas within a range of about 10-300%.
한편, 감광막 측면에 폴리머를 증착함에 있어서, 감광막 전면에 폴리머를 증착한 다음 폴리머 스페이서를 감광막 측면에 형성할 수도 있다.On the other hand, in depositing a polymer on the side of the photosensitive film, the polymer spacer may be deposited on the entire surface of the photosensitive film, and then a polymer spacer may be formed on the side of the photosensitive film.
상기와 같은 방법으로 콘택홀을 형성하면 하부구조의 실리콘패드(4)등과의오정렬을 방지하기 쉽고, 최종 콘택홀의 크기를 어느 정도 확보할 수 있어 콘택홀의 접촉저항을 개선할 수 있다.If the contact hole is formed in the above manner, it is easy to prevent misalignment with the silicon pad 4 of the lower structure, and the size of the final contact hole can be secured to some extent, thereby improving the contact resistance of the contact hole.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하여 2단 기울기를 갖는 콘택홀을 형성하면, 종횡비(aspect ratio)가 다른 콘택홀을 동시에 형성할때 종횡비가 큰 지역에서 하부구조와의 접촉면적(즉, 최종 콘택홀의 크기)이 작아져 저항이 증가하는 문제점을 해결할 수 있다. 동시에 오정렬이 발생하였을때 하부구조와의 단락이 발생할 수 있는 가능성을 없앨 수 있다. 아울러 식각전 폴리머 증착이라는 매우 간단한 방법을 사용하기 때문에 다결정실리콘 스페이서를 이용하는 것과 같은 다른 복잡한 부가공정을 거치지 않아도 되므로 비용을 절감할 수 있다. 그리고 식각장비에서 인시튜(In-situ)로 폴리머를 증착할 수 있기 때문에 신규 장비에 대한 투자도 필요없으며 수율에도 큰 영향을 미치지 않는 경제적 잇점이 있다.According to the present invention, when a contact hole having a two-stage inclination is formed, when the contact holes having different aspect ratios are formed at the same time, the contact area with the substructure (ie, the size of the final contact hole) is small in a region having a high aspect ratio. It is possible to solve the problem of increasing resistance. At the same time, it is possible to eliminate the possibility of a short circuit with the infrastructure when misalignment occurs. In addition, the use of a very simple method of pre-etch polymer deposition saves money by eliminating the need for other complex additional steps such as the use of polysilicon spacers. And since the polymer can be deposited in-situ from the etching equipment, there is no need for investment in new equipment and there is an economic advantage that does not significantly affect the yield.
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