KR930008647A - 마이크로 프로세서 2×(2배) 코어 설계 - Google Patents

마이크로 프로세서 2×(2배) 코어 설계 Download PDF

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KR930008647A
KR930008647A KR1019920018958A KR920018958A KR930008647A KR 930008647 A KR930008647 A KR 930008647A KR 1019920018958 A KR1019920018958 A KR 1019920018958A KR 920018958 A KR920018958 A KR 920018958A KR 930008647 A KR930008647 A KR 930008647A
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core
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frequency
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더블유. 코너리 제임스
알. 버틀러 로버트
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카알 실버맨
인텔 코오퍼레이션
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

마이크로프로세서는 버스속도 또는 그 속도의 배수에서 선택적으로 동작한다. 마이크로프로세서는 마이크로프로세서내의 동작을 위한 클록신호와 버스상의 데이터 전송동작을 위한 버스클록신호를 발생시키는 위상동기루프를 포함한다.
본 발명은 마이크로프로세서코어가 번지/데이타버스와 동일한 주파수 또는 2배의 주파수에서 동작할 수 있게 해준다.

Description

마이크로 프로세서 2X(2배) 코어 설계
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (20)

  1. 데이터를 전송하는 버스를 구비한 컴퓨터시스템내에서 사용되는 마이크로프로세서에 있어서, 상기 마이크로프로세서는: 제1 또는 제2주파수를 가지는 코어클록신호와, 상기 제1주파수를 가지는 버스 클록신호를 발생시키는 클록발생수단; 상기 코어클록신호에 응답하여 상기 데이터를 조작하는 코어유니트; 및 상기 버스클록신호에 응답하여 상기 버스상에 상기 데이터를 보내는 버스제어기 수단으로 구성되며, 상기 제2주파수는 상기 제1주파수보다 빠른 것을 특징으로 하는 마이크로프로세서.
  2. 제 1항에 있어서, 상기 마이크로프로세서는 상기 클록발생수단에 연결되는 전환수단으로 또한 구성되며, 상기 전환수단은 제1위치에 있을 때 상기 제1주파수로, 그리고 제2위치에 있을 때 상기 제2주파수로 상기 코어클록 신호를 발생시키는 상기 클록발생수단을 전환하는 것을 특징으로 하는 마이크로프로세서.
  3. 제 1항에 있어서, 버스클록신호의 펄스폭이 코어클록신호와 동일한 것을 특징으로 하는 마이크로프로세서.
  4. 데이터를 전송하는 버스를 구비한 컴퓨터시스템내에서 사용되는 마이크로프로세서에 있어서, 상기 마이크로프로세서는: 제1 또는 제2주파수를 가지는 코어클록신호와, 상기 제1주파수를 가지는 버스 클록신호를 발생시키는 클록발생수단; 상기 클록발생수단에 연결되어, 제1위치에 있을 때 상기 제1주파수로, 그리고 제2위치에 있을 때 상기 제2주파수로 상기 코어클록신호를 발생시키는 상기 클록발생수단을 전환하는 전환수단; 상기 코어클록신호에 응답하여 상기 데이터를 조작하는 코어유니트; 및 상기 버스클록신호에 응답하여 상기 버스상에 상기 데이터를 보내는 버스제어기 수단으로 구성되며, 상기 제2주파수는 상기 제1주파수보다 빠른 것을 특징으로 하는 마이크로프로세서.
  5. 제 4항에 있어서, 상기 마이크로프로세서는 홀드오프신호를 발생시켜 버스제어기가 구사이클 시작점에서 구사이클 종료점으로 변환하는 것을 막는 홀드오프 발생수단으로 또한 구성되는 것을 특징으로 하는 마이크로프로세서.
  6. 제 5항에 있어서, 상기 전환수단은 정상모드에서 상기 홀드오프발생수단을 비작동시키는 것을 특징으로 하는 마이크로프로세서.
  7. 제 1항에 있어서, 상기 클록발생수단은 : 전(全) 클록신호에 응답하여 코어클록신호를 발생시킴으로서 상기 코어클록신호의 주파수가 전클록신호의 주파수보다 빠르게 하는 커오클록신호 발생수단; 및 상기 코어클록신호 발생수단에 연결되어 코어신호를 수신하고 상기 코어클록신호에 응답하여 버스클록신호를 발생시키는 버스클록신호 발생수단으로 구성되며, 상기 버스클록신호 발생수단은 상기 코어클록신호를 선별하여 상기 버스클록신호를 발생시킴으로써 상기 코어신호가 영향을 받지 않게 하는 것을 특징으로 하는 마이크로프로세서.
  8. 제 1항 제 7항에 있어서, 상기 제2주파수는 제1주파수의 2배인 것을 특징으로 하는 마이크로프로세서.
  9. 제 7항에 있어서, 상기 클록발생수단을 위상동기루프로 구성되는 것을 특징으로 하는 마이크로프로세서.
  10. 제 9항에 있어서, 상기 코오블록발생수단을 구성하는 위상동기루프는 : 상기 전클록신호와 피드백신호를 수신하고 상기 전클록신호와 상기 피드백신호사이의 측정된 위상차에 응답하여 제1신호를 발생시키는 위상검출기수단; 상기 제1신호에 따라 전압제어신호를 발생시키는 전압발생수단; 상기 피드백전압의 레벨에 따라 주파수가 변화하는 코어신호를 상기 전압제어 신호에 응답하여 발생시키는 전압제어되는 오실레이터; 및 상기 코어클록신호에 응답하여 상기 코어클록신호의 배수인 주파수를 가지는 상기 피드백신호를 발생시킴으로써 상기 오실레이터가 상기 전클록신호주파수의 N배인 신호를 만들어내게 하는 주파수분할기수단으로 이루어지는 것을 특징으로 하는 회로.
  11. 제10항에 있어서, 상기 주파수분할기는 : 하나 이상의 상기 코어신호에 응답하여, 제1상태 또는 제2상태를 가지는 선별 신호를 발생시키는 제1논리수단; 및 상기 하나의 코어신호와 상기 선별신호에 응답하여 상기 피드백신호를 발생시키는 제2논리수단으로 구성되며, 상기 제2논리수단은 상기 선별신호가 상기 제1상태에 있을 때 상기 피드백신호를 발생시키고 상기 선별신호가 상기 제2상태에 있을 때 상기 피드백신호를 선별하는 것을 특징으로 하는 회로.
  12. 제10항에 있어서, 상기 주파수분할기는 상기 버스클록신호를 발생시키는 것을 특징으로 하는 회로.
  13. 전클록신호에 의해 클록되는 마이크로프로세서의 코어가 번지 및 데이터버스의 주파수의 N배에서 동작할 수 있게 하는 회로에 있어서, 상기 회로는 : 상기 전클록신호와 피드백신호를 수신하고 상기 전클록신호와 상기 피드백신호 사이의 측정된 위상차에 응답하여 제1신호를 발생시키는 위상검출기수단; 상기 제1신호에 따라 전압 제어신호를 발생시키는 전압발생수단; 상기 피드백전압의 레벨에 따라 주파수가 변화하는 코어신호를 상기 전압 제어 신호에 응답하여 발생시키는 전압제어되는 오실레이터; 및 상기 하나의 코어신호와 상기 선별신호에 응답하여 상기 버스클록신호를 발생시키는 제2논리수단으로 구성되며, 상기 제2논리수단은 상기 선별신호가 상기 제1상태에 있을 때 상기 버스클록신호를 발생시키고 상기 선별신호가 상기 제2상태에 있을 때 상기 코어클록신호의 배수의 주파수를 가진 상기 버스제어신호를 선별하며, 상기 버스제어신호중 하나는 상기 피드백신호가 되어서, 상기 오실레이터가 상기 전클록신호주파수의 N배인 코어클록신호를 만들어내게 하는 것을 특징으로 하는 회로.
  14. 제13항에 있어서, 상기 제2논리수단은 상기 버스제어신호를 하나씩 걸러 선별하는 상기 선별신호를 발생시킴으로써, 상기 피드백신호가 상기 전클록신호주파수의 2배로 코어클록신호를 만들도록 상기 오실레이트를 구동시키는 것을 특징으로 하는 회로.
  15. 제13항과 제14항에 있어서, 상기 회로는 또한 정상모드와 고속모드 사이에서 코어를 전환하는 전환수단으로 구성되는 것을 특징으로 하는 회로.
  16. 제13항과 제14항에 있어서, 상기 회로는 또한 홀드오프신호를 발생시키어 버스 제어기가 구사이클 시작점에서 구사이클 종료점으로 변환하는 것을 맞는 홀드오프 발생수단으로 구성되는 것을 특징으로 하는 회로.
  17. 제16항에 있어서, 상기 전환수단은 정상모드에서 상기 홀드오프 발생수단을 비작동시키는 것을 특징으로 하는 회로.
  18. 데이터를 전송하는 버스를 구비한 컴퓨터 시스템내에서 사용되는 마이크로프로세서에 있어서, 상기 마이크로프로세서는 : 상기 데이터를 조작하는 코어; 및 상기 버스상에 상기 데이터를 보내는 버스제어기 수단으로 구성되며, 상기 코어는 상기 버스보다 빠르게 동작함으로써 버스로 하여금 상기 코어가 조작하는 것보다 많은 데이터를 수용할 수 있게 하는 것을 특징으로 하는 마이크로프로세서.
  19. 제18항에 있어서, 상기 버스주파수에 대한 클록펄스의 펄스폭은 상기 코어주파수에 대한 클록펄스의 펄스폭과 동일한 것을 특징으로 하는 마이크로프로세서.
  20. 제19항에 있어서, 버스클록신호는 1/4 튜티클록사이클인 것을 특징으로 하는 마이크로프로세서.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920018958A 1991-10-17 1992-10-15 마이크로프로세서 2곱하기(2배) 코어 설계 KR100265218B1 (ko)

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US77857591A 1991-10-17 1991-10-17
US778,575 1991-10-17

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KR930008647A true KR930008647A (ko) 1993-05-21
KR100265218B1 KR100265218B1 (ko) 2000-09-15

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ITMI922317A1 (it) 1993-04-18
JPH05233275A (ja) 1993-09-10
US5630146A (en) 1997-05-13
GB2260631B (en) 1995-06-28
FR2682785A1 (fr) 1993-04-23
FR2682785B1 (ko) 1995-02-17
US5481731A (en) 1996-01-02
DE4235005C2 (de) 2002-11-28
US5634117A (en) 1997-05-27
ITMI922317A0 (it) 1992-10-08
US5884068A (en) 1999-03-16
DE4235005A1 (de) 1993-04-22
GB9218302D0 (en) 1992-10-14
CN1130646C (zh) 2003-12-10
IT1255851B (it) 1995-11-17
KR100265218B1 (ko) 2000-09-15
CN1071525A (zh) 1993-04-28
GB2260631A (en) 1993-04-21
US5537581A (en) 1996-07-16

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