KR920020616A - 위치맞춤방법 및 장치 - Google Patents

위치맞춤방법 및 장치 Download PDF

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Publication number
KR920020616A
KR920020616A KR1019920005700A KR920005700A KR920020616A KR 920020616 A KR920020616 A KR 920020616A KR 1019920005700 A KR1019920005700 A KR 1019920005700A KR 920005700 A KR920005700 A KR 920005700A KR 920020616 A KR920020616 A KR 920020616A
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KR
South Korea
Prior art keywords
alignment
predetermined
mark
substrate
alignment mark
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KR1019920005700A
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English (en)
Inventor
후미오 미스노
노보루 모리구찌
세이이찌로 시라이
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 가나이 쯔또무
Publication of KR920020616A publication Critical patent/KR920020616A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/304—Controlling tubes by information coming from the objects or from the beam, e.g. correction signals
    • H01J37/3045—Object or beam position registration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/682—Mask-wafer alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Analytical Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electron Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

위치맞춤방법 및 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예인 위치맞춤장치의 구성을 설명하는 설명도,
제2도는 그 맞춤장치의 위치맞춤마크노출수단을 설명하는 설명도,
제3도는 그 위치맞춤장치의 위치맞춤수단을 설명하는 설명도.

Claims (8)

  1. 기판상에 형성된 1개 또는 2개 이상의 위치맞춤마크중의 소정의 위치맞춤마크의 위치좌표를 검출하고, 그 위치좌표에 따라서 기판의 위치맞춤을 실행할때에 상기 소정의 위치맞춤마크의 위치검출공정에 앞서서 상기 소정의 위치맞춤마크를 피복하는 소정의 막부분을 제거하고, 상기 소정의 위치맞춤마크를 노출시키는 공정을 갖는 위치맞춤방법.
  2. 특허청구의 범위 제1항에 있어서, 상기 소정의 위치맞춤마크를 피복하는 소정의 막부분을 에너지빔을 사용한 가스어시스트에칭법에 의해서 제거하는 위치맞춤방법.
  3. 특허청구의 범위 제2항에 있어서, 상기 에너지빔은 레이저빔, 전자빔 또는 이온빔인 위치맞춤방법.
  4. 특허청구의 범위 제3항에 있어서, 상기 기판은 반도체웨이퍼인 위치맞춤방법.
  5. 기판상에 형성된 1개 또는 2개 이상의 위치맞춤마크중의 소정의 위치맞춤마크의 위치좌표를 검출하는 마크위치검출부와 상기 위치좌표에 따라서 기판의 위치맞춤을 실행하는 위치맞춤부를 갖는 위치맞춤수단의 전단에 상기 소정의 위치맞춤마크를 피복하는 소정의 막부분을 제거하기 위한 위치맞춤마크노출수단을 마련한 위치맞춤장치.
  6. 특허청구의 범위 제5항에 있어서, 상기 위치맞춤마크노출수단은 상기 맞춤마크를 피복하는 소정의 막부분에 대해서 에너지빔을 조사하는 빔조사수단과 상기 에너지빔의 조사위치에 소정의 에칭가스를 공급하는 가스 공급수단을 갖는 위치 맞춤장치.
  7. 특허청구의 범위 제6항에 있어서, 상기 가스공급수단은 여러종류의 가스를 전환해서 공급하기 위한 전환기구를 갖는 위치맞춤장치.
  8. 특허청구의 범위 제6항에 있어서, 상기 위치맞춤수단은 상기 빔조사수단 및 가스공급수단을 여러개 갖는 위치맞춤장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920005700A 1991-04-19 1992-04-06 위치맞춤방법 및 장치 KR920020616A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP8805291 1991-04-19
JP91-088052 1991-04-19
JP3176492A JPH053143A (ja) 1991-04-19 1991-07-17 位置合せ方法および装置
JP91-176492 1991-07-17

Publications (1)

Publication Number Publication Date
KR920020616A true KR920020616A (ko) 1992-11-21

Family

ID=26429492

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005700A KR920020616A (ko) 1991-04-19 1992-04-06 위치맞춤방법 및 장치

Country Status (3)

Country Link
US (1) US5405810A (ko)
JP (1) JPH053143A (ko)
KR (1) KR920020616A (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2595885B2 (ja) * 1993-11-18 1997-04-02 日本電気株式会社 半導体装置およびその製造方法
JP2669391B2 (ja) * 1995-03-30 1997-10-27 日本電気株式会社 半導体装置
KR970003401A (ko) * 1995-06-20 1997-01-28 김주용 디스톨션 체크용 레티클
KR100199371B1 (ko) * 1995-06-24 1999-06-15 김영환 디펙트 모니터링용 레티클
US5545570A (en) * 1995-09-29 1996-08-13 Taiwan Semiconductor Manufacturing Company Method of inspecting first layer overlay shift in global alignment process
JP2967755B2 (ja) * 1997-04-17 1999-10-25 日本電気株式会社 半導体装置の製造方法
US5956564A (en) 1997-06-03 1999-09-21 Ultratech Stepper, Inc. Method of making a side alignment mark
US6100157A (en) 1998-06-22 2000-08-08 Oki Electric Industry Co., Ltd. Formation of alignment mark and structure covering the same
JPH1126361A (ja) * 1997-06-27 1999-01-29 Oki Electric Ind Co Ltd アライメントマーク及びアライメントマーク用凹部の隠蔽方法
EP0892433A1 (en) * 1997-07-15 1999-01-20 International Business Machines Corporation Method of forming an alignment mark in a semiconductor structure
US6476499B1 (en) 1999-02-08 2002-11-05 Rohm Co., Semiconductor chip, chip-on-chip structure device and assembling method thereof
CN1286146C (zh) 2001-03-09 2006-11-22 株式会社东芝 电子装置的制造系统
JP4537603B2 (ja) * 2001-03-09 2010-09-01 株式会社東芝 半導体装置の製造方法
US20030138709A1 (en) * 2001-11-09 2003-07-24 Burbank Daniel P. Wafer fabrication having improved laserwise alignment recovery
US7288466B2 (en) * 2002-05-14 2007-10-30 Kabushiki Kaisha Toshiba Processing method, manufacturing method of semiconductor device, and processing apparatus
US7171035B2 (en) * 2002-11-06 2007-01-30 Texas Instruments Incorporated Alignment mark for e-beam inspection of a semiconductor wafer
US7150811B2 (en) * 2002-11-26 2006-12-19 Pei Company Ion beam for target recovery
FR2869459B1 (fr) * 2004-04-21 2006-08-04 Commissariat Energie Atomique Realignement entre niveaux apres une etape d'epitaxie.
JP4389932B2 (ja) * 2004-05-17 2009-12-24 日立金属株式会社 薄膜磁気ヘッド用基板およびその製造方法
WO2011024289A1 (ja) * 2009-08-28 2011-03-03 富士通株式会社 光学部品製造方法および光学部品製造装置
US9497862B2 (en) * 2011-01-30 2016-11-15 Nantong Fujitsu Microelectronics Co., Ltd. Packaging structure
CN103474583A (zh) * 2013-09-24 2013-12-25 京东方科技集团股份有限公司 柔性显示基板及其制备方法、柔性显示装置

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* Cited by examiner, † Cited by third party
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US4414749A (en) * 1979-07-02 1983-11-15 Optimetrix Corporation Alignment and exposure system with an indicium of an axis of motion of the system
JPS56122128A (en) * 1980-02-29 1981-09-25 Telmec Co Ltd Positioning system for printing device of semiconductor or the like
JP2637412B2 (ja) * 1987-02-25 1997-08-06 キヤノン株式会社 位置あわせ方法
JPH0770575B2 (ja) * 1987-05-25 1995-07-31 松下電子工業株式会社 半導体装置
US4936930A (en) * 1988-01-06 1990-06-26 Siliconix Incorporated Method for improved alignment for semiconductor devices with buried layers

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Publication number Publication date
JPH053143A (ja) 1993-01-08
US5405810A (en) 1995-04-11

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